Re: [oc] SoC bus review

["Richard Herveille" <Richard.Herveille@pie.nl>]

Hi Rudi,

ARM has a pattent on the AMBA bus. I looked it up and made a copy of their
claims.


I claim:

1. An integrated circuit comprising:

a plurality of data handling devices interconnected to exchange data by an
interconnection bus during a first mode of operation, said data handling
devices comprising one or more bus master data handling devices and one or
more bus slave data handling devices; and

diagnostic control means, responsive to a diagnostic device external to said
integrated circuit, comprising a diagnostic bus master data handling device
for controlling one or more of said data handling devices to exchange
diagnostic data with said diagnostic device via said interconnection bus
during a second, diagnostic, mode of operation.

2. An integrated circuit according to claim 1, comprising:

arbitration means, responsive to a request for control of said
interconnection bus by one or more of said bus master data handling devices,
for allocating control of said interconnection bus to a bus master data
handling device in dependence on a predetermined priority order associated
with said bus master data handling devices.

3. An integrated circuit according to claim 2, in which said diagnostic
control means has a higher priority, in said predetermined priority order,
than all other bus master data handling devices connected to said
interconnection bus.

4. An integrated circuit according to claim 1, in which said diagnostic
control means comprises means for selectively controlling all other data
handling devices connected to said interconnection bus to operate as bus
slave devices.

5. An integrated circuit according to claim 1, in which said diagnostic data
comprises one or more successive diagnostic vectors according to a
predetermined diagnostic procedure associated with a data handling device
under test.

6. An integrated circuit according to claim 5, in which the one or more
diagnostic vectors comprise an address vector for selecting a data handling
device to be tested.

7. An integrated circuit according to claim 1, in which said integrated
circuit is operable under the control of successive cycles of a clocking
signal.

8. An integrated circuit according to claim 7, in which said diagnostic
control means is responsive to a control signal received from the diagnostic
device during a current cycle of the clocking signal, to control one or more
of said data handling devices to exchange diagnostic data with said
diagnostic device via said interconnection bus during subsequent cycles of
said clocking signal.

9. An integrated circuit according to claim 1, comprising a data buffer,
said data buffer providing an external data bus enabling transfer of data
between said interconnection bus and data handling devices external to said
integrated circuit; and in which said diagnostic control means is operable
to place said external data bus into a high impedance state.

10. A method of operation of an integrated circuit having a plurality of
data handling devices interconnected to exchange data by an interconnection
bus during a first mode of operation, said data handling devices comprising
one or more bus master data handling devices and one or more bus slave data
handling device said method comprising the step of:

controlling one or more of said data handling devices with a diagnostic bus
master data handling device to exchange diagnostic data with a diagnostic
device external to said integrated circuit via said interconnection bus
during a second, diagnostic, mode of operation.


(Taken from US pattent 5,525,971)

As with all US pattents these claims are as broad as they can be. In fact
the above stated claims can cover (parts of) CoreConnect and Wishbone as
well.
I don't think we would get into trouble using the AMBA bus, but we would get
into trouble when we modified it in anyway and claimed it as a new bus. But
than again I am no lawyer :)

Richard

>
> Attached is a small doc I created of three SoC busses.
>
> It is basically a comparison, and my personal feelings about
> the three busses.
>
> I would welcome any comments and suggestions as well as a
> friendly discussion on the doc !
>
> Hopefully we can all agree on one SoC bus and jointly use it for
> all future core developments.
>
> Best Regards,
> rudi
>