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Re: [oc] NEW PROJECT PROPOSAL(robotic arm controller )
>I would like to see a DC motor driver core for the Xilinx spartan II. It
>would implement
>PID control for six or so DC motors.
>
>It would have a serial interface (or usb???) to a host, pwm and direction
>signals for each motor, and a quadrature
>encoder input for each motor. The serial interface would take commands,
>such as relative
>and absolute position and drive each motor accordingly. I would guess the
>easiest way to do this would be
>to synthesize a 16 or 32 bit processor on the fpga, along with quadrature
>decoder core modules.
Do you mean I/Q decoders ? There's a cordic core (rectangular to polar
conversion) on OpenCores.
>I am quite a long way from doing this by myself (just learning verilog), but
>it is on my wish list....
>
>Richard
>
>----- Original Message -----
>From: "sathish sathish" <sathishr@rediffmail.com>
>To: <cores@opencores.org>
>Sent: Tuesday, April 17, 2001 11:09 AM
>Subject: [oc] NEW PROJECT PROPOSAL(robotic arm controller )
>
>
> > hello,
> > I have Successfully developed a robotic arm controller (stepper motor
>controller core) in VHDL.I want to publish it in www.opencores.org.please
>permit me to do it. .here with i present the short describtion of my core.
> >
> > core description:
> > robotic arm controller is developed in VHDL and it is fitted in Cypress
>C22V10 PAL IC.
> > Synthesize Tool:Cypress Warp 4
> > IC :PAL C22V10
> >
> > Functionality:
> > to control the stepping speed of stepper motor
> > by full step mode
> > half step mode.
> > to control the stepping direction of stepper motor
> > by clockwise mode
> > anticlockwise mode.
> >
> > Interfacing Card:
> > to drive the stepper motor the collector of 4 darlington pair transistors
>are connected to the windings of motor,a free-wheeling diode is connected
>across each winding for fast switching.
> >
> > INPUTS:
> > clock is given from clock generatorIC4060 to PAL IC .
> > speed & direction control mode is selected and conrolled by input
>switches of this robotic arm controller hardware board
> >
> > NOTE:
> > time delay between each switching sequence should be 1 to 5msec.
> > for implementing this design in fpga use appropriate clock diveder.
> >
> > If you have intreset in it,Please contact me at sathishr@rediffmail.com
> >
> > with regs,
> > sathish kumar.r
> >
> > _____________________________________________________
> > Chat with your friends as soon as they come online. Get Rediff Bol at
> > http://bol.rediff.com
> >
> >
> >
> >
> >