Re: [oc] UART16550 core

["Carl van Schaik" <carl@openfuel.com>]

> Great.
>
> Is the host interface wishbone compatible?
I hope so :-)

> If I understood correctly you took the UART16650 from the opencores when
you
> started, and chenged it a bit, right? Do you have any testbenches already
> avaliable?
Original ideas taken from the UART16550 but a lot is different too.

I don't have access to Model Sim, hopefully we will get a license soon.
I only have some vector tests that I made with the Xilinx Timing analyser.

regards
Carl van Schaik

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