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[oc] Re: firewire info
On Thu, Aug 02, 2001 at 10:52:11PM -0400, Jim W wrote:
> Yes, I am working on it ;). I am reading some literatures and hopefully will
> pull together a requirement document soon so that we know what we are
> shooting for. I welcome very much any help you can offer.
Some suggestions I can make:
A 1394 interface consists of two parts: physical layer and link layer.
The Phy requires special signal generation facilities and is not
implementable in a general FPGA, I think. That is not the interesting
part anyway, the Phy is pretty much always the same (standardized
interface) and there is not much to win over an off-the-shelf chip.
Some of the bigger FPGAs have special differential signal handling
hardware, so a Phy might be implementable directly with them.
The interesting part, the link layer, can be further split into two
parts (which is how the available chips look like): the core 1394
handling state machines plus FIFOs for packets to send and receive, and
the programmer visible frontend (including a DMA engine). I suggest
separating these two parts into two cores, the link layer core (of which
there will be one) and the frontend (of which there can be many;
Wishbone DMA, PCI DMA, non-DMA 8-bit micro controller frontend, anything
else desired).
I can help with suggestions and some 1394 knowledge, but I don't think I
can spare the time to work much on this project (although it would be
interesting). Especially if it's done in Verilog, of which I know
nothing.
--
Andreas E. Bombe <andreas.bombe@munich.netsurf.de> DSA key 0x04880A44
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