[oc]:Help on Backend Verification

[khong lin pang <mailtopang@yahoo.com>]

Hi PeeKay,

Thanks for giving me some direction. I have never
wrote any C but i do understand the logic when i see
one. I am more of an assembly and C++ person. There
are not many Verilog classes to attend here, except
for some training classes on Synopsys tools conducted
by the company that sells us Synopsys. ( and i have
yet to attend one ) What i think i need now is to know
the general flow of IC design. what file is this, when
was it generated and what should be done on every
stages. 

I made a mistake of taking too long to study all the
verilog codes and until now, i still don't quite
understand how certain portion goes. The documentation
is little and many variables unexplained. ( And it was
wrote by more than 4 person )

Let keep things short.

The company that is suppose to do the layout and
masking later on return three files, 

'  *.v, *.sdf_data, *.str  ' 

I read the *.v file into design_analyzer and all i see
is gate level schmatics. Then i tried to read
*.sdf_data but the following errors occurs -

design_analyzer>......
Error in SDF File /direct/file.sdf_data Line 9: syntax
error at or near token 'TIMESCALE'

The reason i did that is because some colleague says
that perhaps i could open up the schematics and
compare the internal connection and then link it to
the test bench. Is this the correct way?

You have mention that all I need is to change the
modules that the previous test bench refers to. I will
do that ( changing the include files ) and test it
again. But what i heard from others is that i really
need to search for all the equivalent probe inside the
new netlist. It doesn't make sense for the test bench
to read from a non existent node. 

What should i do from here?
1. Write a new test bench, but this time treat the
controller as a black box and only probe for the pins
that are coming out of the controller, but that
wouldn't be thorough.
2. Search for the equivalent name of the same node.
say 
       eeprom_data to .A2(NET1234)
- how to do that?

Hopefully, PeeKay or anyone could give me direction
and the usual practice. Time may be short, but i would
rather spend some time verifying it than to simply do
it.

Thanks.

Rgds,

Pang



 --- Peekay Chan <peekay@synopsys.com> wrote: > 
> Hi Khong,
> 
> - Do you have any HDL or C language background?  Now
> one month into Verilog,
> you probably have some ideas of what the language
> does.  However, I do
> suggest you take 3 days to take an advance Verilog
> training class, there are
> consulting companies and also Synopsys has those
> training class.
> 
> - You should also have the pre-layout testbench
> environment that you can
> use.  The only thing about backend simulation is
> that the timing is more
> accurate and runs SLOWER.  You should only need to
> change the top module.
> 
> - 8051 is not an awefully fast device, and you
> shouldn't have much timing
> skews in the backannoted netlist.
> 
> - Just want to point out that 50% + of most projects
> nowadays is being spent
> on verification.  Don't under estimate your
> schedule.
> 
> Cheers
> 
> Peekay
> 
> -----Original Message-----
> From: owner-cores@opencores.org
> [mailto:owner-cores@opencores.org]On
> Behalf Of khong lin pang
> Sent: Tuesday, October 23, 2001 6:57 PM
> To: cores@opencores.org
> Cc: mailtopang@yahoo.com
> Subject: [oc]:Help on Backend Verification
> 
> 
> Hi all,
> 
> This is my first posting to the list, please point
> out
> any errors like wrong tagging or subject. I am
> extremely fresh in this area but i am forced to
> continue ( alone ) a project started by a group of
> people. I had no prior training in Synopsys or
> Verilog, but i have tried learning up Verilog for
> the
> past one month. If there are any active list for
> beginner and desperate people like me, please tell
> me.
> 
> The problem -
> 
> - This project is basically a microcontroller, with
> a
> 8051 core and some others component like serialX,
> watchdog, real time clock, and general purpose IO.
> - The verilog coding was finished some time ago and
> test bench was written to test each component and
> the
> whole controller as well. It tested good. ( Is this
> what you call front end design and front end
> verification? )
> - Now the net list was generated and it was send to
> another vendor for layout purposes. The vendor
> return
> two netlist files, one is the sdf and the other...
> timing file?
> - Now we are suppose to verify again on the return
> file to see if it is correct.( Is this call backend
> verification? ) But the problem is how are we going
> to
> change our test bench when all the naming
> conventions
> has changed? Usually what should be done to be able
> to
> test it again?
> 
> - I am running out of time, but nobody seems to
> care,
> those engineers that help to develope the system has
> other project to handle and i guess when the
> deadline
> comes i will be the person that everyone point their
> fingers to. Please help.
> 
> 
> Rgds,
> 
> Dmm
> 
> 
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>  


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