Re: [oc] Re: Opencores Design Guidelines

[Rudolf Usselmann <rudi@asics.ws>]

Damjan,

the text looks good, EXCEPT for the synchronizer_flop reference.

Let me explain why:
1) The synchronizer flop is a single RTL flop.
2) The intention, as I understand it, is to use this RTL model to
replace synchronizer flops in a gate-level simulation to avoid
unknown output when setup/hold timing is violated (which can
occur during synchronization).

I feel that this sync flop thingie is VERY confusing.

Lawrence, perhaps you can clarify this somewhere and document
what the real intention is, and warn people that a single flop will not
do the job ...

Thanks,
rudi

On Sunday 11 November 2001 10:31, you wrote:
> Rudi,
>
> is this ok:
>
> Strong Recommendation: Signals that cross different clock domains
> should be sampled twice in destination clock domains (double sampling is
> a MUST). See synchronizer_flop in OpenCores CVS in module common.
>
> Prevents meta-stability state.
>
> To make netlist verification easier, you should use one module (i.e.
> sync.v, sync.vhd) that will have in, out and clock interface and the
> first flip-flop should
> have a unique name as this flip-flop will have timing violation. If it
> has unique
> name, it is easier to trace it and "change" it to not pass X's.
>
> Also it should be clear that you pass ONLY the control signal and not the
> data
> bus etc.
> <<
>
> For the record, I did not write 3.3.1. If above is not ok, send me a text
> that you want to see as 3.3.1. The only thing I ask to refer to
> synchronizer flop in the CVS.
>
> regards,
> Damjan
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