Re: [oc] Anyone using VHDL procedures with Xilinx Webpack?

[Scott Zuk <sz@telusplanet.net>]

Hi,

This message wasn't directed at me however I think I might be able to help 
here.  The main problem is that you are performing signal assignments to cs2n 
and cs3n in two different places in the function.  This causes problems with 
simulation even though the assignments are mutually exclusive in your 
if..else statement (maybe someone else can give a more detailed explanation). 
You can get around this by declaring a couple of temporary variables in your 
function and only performing signal assignment ONCE:

impure function PIO_register_write ( p_DA : std_logic_vector (2 downto 0);
 p_cs : integer ;   p_data : std_logic_vector (7 downto 0)  ) RETURN bit is

 VARIABLE temp_cs1n, temp_cs3n : std_logic;  -- declare some temp vars 

 begin
 	DA 		<= p_DA ;
 	if (p_cs = 1) then
 		-- register is in block 1
 		temp_cs1n 	:= '0' ;	-- uses variable assignment (occurs immediately)
 		temp_cs3n	:= '1' ;
 	else
 		-- register must be in block 3
 		temp_cs1n	:= '1' ;
 		temp_cs3n	:= '0' ;
 	end if;
 	iocs16n  <= '1' ;	-- only 8 bit register transfers
 	hi_byte  <= (others => '0') ;
 	lo_byte 	<=	p_data ;
	cs1n <= temp_cs1n;	-- perform signal assignments once
	cs3n <= temp_cs3n;
 	return '1' ;
 end function PIO_register_write ;


Hope some of this helps.

~Scott
On December 7, 2001 07:48 pm, you wrote:
> Jim,
>
> here is my biggest and most complicated function to date. Most people will
> probably recognise it as a simple function to let me write a byte to an IDE
> device's register via the PIO scheme. As the other function contains only
> pin assignments and no conditional logic this is the likely cause of
> Webpacks failure to process the VHDL properly.
>
> impure function PIO_register_write ( p_DA : std_logic_vector (2 downto 0);
> p_cs : integer ;   p_data : std_logic_vector (7 downto 0)  ) RETURN bit is
> begin
> 	DA 		<= p_DA ;
> 	if (p_cs = 1) then
> 		-- register is in block 1
> 		cs1n 		<= '0' ;
> 		cs3n 		<= '1' ;
> 	else
> 		-- register must be in block 3
> 		cs1n 		<= '1' ;
> 		cs3n 		<= '0' ;
> 	end if;
> 	iocs16n  <= '1' ;	-- only 8 bit register transfers
> 	hi_byte  <= (others => '0') ;
> 	lo_byte 	<=	p_data ;
> 	return '1' ;
> end function PIO_register_write ;
>
> If you tell me where in this function the error maybe then I will be so
> much the wiser. I'm not using macros or any string substitution system.
> When having them as procedures failed miserably I converted them to
> functions (then impure functions) and just return a '1' every time to
> validate them as functions versus procedures. Even as functions they fail
> to compile due to "exceptional errors" reported by Webpack.
>
> I'm going to give up on coding VHDL by hand and just develop my Buffy-C
> (working title for my version of Handel-C) then I can write a bloody IDE
> interface in 30 minutes not 30 days (plus the C one will work). I've
> probably spent %5 of my VHDL time putting new lines into the VHDL file and
> the other 95% getting Webpack to allow it to compile. I realise I am a
> newbie at VHDL but as I think up all my new projects in C terms so I want
> to code it in C as well. Trying to convert mentally from C to VHDL is too
> much for my set-in-its-ways brain to handle.
>
> Paul
>
> PS The code generated by Buffy-C doesn't contain any functions/procedures
> and it never will until VHDL compilers can happily compile them.
>
>
>
>
> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of Jim Dempsey
> Sent: 07 December 2001 16:52
> To: cores@opencores.org
> Subject: Re: [oc] Any using VHDL procedures with Xilinx Webpack?
>
>
>
> ----- Original Message -----
> From: "Paul McFeeters" <paul.mcfeeters@ntlworld.com>
> To: <cores@opencores.org>
> Sent: Thursday, December 06, 2001 4:52 PM
> Subject: RE: [oc] Any using VHDL procedures with Xilinx Webpack?
>
> > Jim,
> >
> > if it is a recursion then I can't see it. Each procedure is literally
> > just around 5 lines each "pin <= value" format, no special
> > procedure/function calls at all. One procedure does have a "if param =
> > value then -- else -- end if" statement and uses an alias to reference
> > the low byte in a word
>
> but
>
> > nothing more than that, definitely nothing I would even suspect as 'a
>
> little
>
> > dodgy'. All of these statements in their current form were used fine in
>
> the
>
> > expanded code so still clueless as to why Webpack should bomb.
>
> Some times the littlest code segments produce the "can't see the forest for
> the trees" effect.
>
> Memory overflows on small code segments are commonly caused by
> recursion. An example of this in C/C++ is where a #define macro
> somehow rereferences itself or one of it's subordinates.
>
> I am not up on this form of programming (VHDL) however if for example
> you have a proceedure (macro?) called "ZooBie" and if the declaration
> of macro "ZooBie" contains
>
>     "if param = ZooBie then -- else -- end if"
>
> You can see how this would expand forever.
> To help locate this if your VHDL "compiler" has conditional
> statement you could enable and disable sections of your code.
> *** Note, some compilers expand comments and conditioned
> out code. so you may also have to sprinkle in invalid characters
> to prevent the recursion from occuring within a comment. e.g.
>
>     #if(TRUE==FALSE)
>     "if pa!!!ram = Zoo!!!Bie then -- else -- end if"
>     #endif
>
> Hope this leads you to a resolution
>
> Oh, anicdotal information.
>
> Several years ago I used Borland C++ (still do) and the version
> of the compiler had a "bug" wherein if a particular token sequence
> was split across compiler I/O buffer boundaries that an error would
> be introduced into the code. Adding a well place extra space
> character in a comment would usualy fix the problem.
>
> Jim Dempsey
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