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Re: [oc] Sequential processing in VHDL? Whats the best way todo it?
>Hi,
>
>I have started working on my own version of Handel-C to convert C into VHDL
>(couldn't find $75,000 laying around the house). The first problem I
>obviously encountered was that VHDLs sequential processes don't work as
>high-level programmers would expect them to. I'm using signals for global
>variables but in VHDL sequential logic processes the signals are not
>actually updated until the process finishes. Hence as we all know the
>following example IF statement always fails.
>
>-- on entry x is always 10
>check_x : process (clock)
>begin
> x <= 6 ;
> if (x = 6) then
> -- this code section will never be called as x will only change after the
>process has finished
> end if ;
>end process ;
>
or something like this - if you actually need the signal externally to the process.
process (clk )
VARIABLE varx: INTEGER;
begin
varx :=6;
if (x=6) then ...
end if;
x<=varx;
end process;
Beware though, you can create very deep logic this way.
>I presume this is why even Celoxica have to synchronise their Handel-C code
>with a clock. The best way I have found of doing it so far is to adopt an
>approach similar to how I presume CPU cores do it. This is my plan so far,
>each C statement will need its own process. The following example is my best
>(and working yippee) way of doing it.
>
<snip>
Clocked processes tend to follow the template
process(clk, resetn)
variable PC: integer range 0 to some_big_number;
begin
if resetn = '0' then
PC := 0
-- initialise lots of variables
elsif rising_edge(clk) then
case PC:
when 0 => --do something
when 1 => do something else
end case;
PC := PC + 1;
end process.
This will again create very deep logic, but may work.
My thought would be to create one of these for each section of code that needs to have "sequential" behaviour. Each section will then operate in parallel as signified by the par{} constructy in Handel-C. Or however you choose to express paralellism.
>
>If anybody has a better, neater or faster way of doing it then I would love
>to know it. I've found the source code for a mini-C compiler so will use
>that for lexical parsing and once I have the VHDL backend sorted I'll be
>calling for guinea pigs.
>
Which platform? I may be able to test...
>I did think that if you made the process itself sensitive to 'PC' then once
>the process has finished and thus PC is updated it would then call the
>process again thus making things easier. Unfortunately the error that comes
>from Webpack leaves me in no uncertain terms that it can't be done that way.
>If anybody thinks that another synthesising tool may allow it then please
>again let me know.
>
Webpack is not a 'real' simulator AFAIK. Xilinx and Altera both offer limited versions of Modelsim, but I reckon you'll reach the 500 line limit fairly quickly. There are some free (for some senses of the word) simulators about, which I think are text only, but that may be fine for a start off. Esp. if you get printf's in there!
HTH!
Martin
--
Martin Thompson BEng(Hons) CEng MIEE
TRW Conekt
Stratford Road, Solihull, B90 4GW. UK
Tel: +44 (0)121-627-3569 - martin.j.thompson@trw.com
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