Re: [oc] Processor Instruction reply for Andreas

[Rudolf Usselmann <rudi@asics.ws>]

On Tuesday 11 December 2001 01:31 am, you wrote:
> Andreas,
>
> > > Old Way:
> > >
> > > 	CMP AX,$2000
> > > 	JC  #4000
> > >
> > > Two instructions to do that? Why use two clock cycles for that? Can't
> > > we just have a CMPJxx instruction? Takes two values/register
> > > combinations and based upon the results of the comparisons
> > >  jumps to the destination or not.
>
> > There are two things to be done.  A subtraction and a conditional jump.
> > Just because you put them in the same instruction doesn't make them in
> > one cycle.  If they do execute in one cycle, I guess the cycles on that
> > machine are generally longer.
>
> Wrong. I tested it out and it makes simple sense. When a compare is done
> then the HDL copies the value of '1' into the relevant flag. As any HDL
> programmer will tell you copying a 32bit value versus 1 bit doesn't take
> a ps longer so my way is quicker.

You are both right. I think Paul, you missed Andreas point.

The problem with a compare and jump instruction is that it is rather 
complex. You must find the best tradeoff for your implementation.

The compare is usually a subtracter. After you are done with the 
subtraction you do a conditional jump.

If your clock is 1 MHz and you are using 0.18u standard cell, it's not a 
problem. But if you want to have your CPU run at 500 MHz, it's tough.
You have two options: 1) heavily pipeline the instruction; 2) break it up 
in to two instructions.

The advantages and disadvantages are:

For 1:
+ single instruction, saves program space
- very long pipeline, branches execute many cycles after
   issuing (long delay slots)
- Depending on implementation, may take different number of
  cycles to execute, when a branch is taken, vs. not taken.

For 2:
- Two instructions, need larger program memory
+ short pipeline
+ faster execution

To summaries, a RISC architecture typically tries to keep it's instructions
very simple and easy to execute. The goal for a RISC is to execute a
small number of instructions at a very high speed. This results in overall
faster execution, even though one might argue that the complex CISC
instructions "do more". Compared to a RISC, a CISC is typically alot
slower.

rudi
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