RE: [oc] Verilog vs VHDL

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Brad,

all I can say is that I started programming in VHDL as it appeared the more
popular language. It was fairly easy to get a simple program in it up and
running. Unfortunately I then found practically all the professional (as in
doing it for a living) HDL programmers I spoke to code in Verilog. So I took
a look at Verilog instead, haven't looked back yet. If you know how to code
simple C programs then Verilog is rather like a wacky version of C. You still
have to used to recurrent processes and bit manipulation slightly differently
but generally its a smooth transition well it was for me anyway.

PS I coded my VHDL programs in Webpack and they never worked properly. Since I
switched to Verilog (still using Webpack) so I could ask advices from the pros 
all my programs have worked 100% as expected. I don't look back.

Paul

> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of brad@tinyboot.com
> Sent: 14 December 2001 17:55
> To: cores@opencores.org
> Subject: [oc] Verilog vs VHDL
> 
> 
> Since some cores on Opencores are expressed in VHDL and 
> others are expressed in Verilog, I'm wondering which language I 
> should code new hardware in. I know VHDL but maybe Verilog 
> would be more productive. 
> 
> How good a job do translators do when going from one language 
> syntax to the other. I would like to start with a source language 
> that translates in the least messy way.
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