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Re: [oc] newbie to wishone
Seems like this email never reached the mailing list.
Therefore a new try.
> Hi all,
> I am trying to write a converter between an AMBA master and a
> WISHBONE slave. If it allready exists, please let me know.
> I have a problem with the wishbone specification.
It is (almost) finished.
I attached what I've done so far to this email.
>
> 1) the master drives everything on the rising edge, but what about the
> slave? If everything (data, address and control) must be driven in oe
> clock cycle, is the slave then asynchronous, or does it read and drive on
> the falling edge of the clock?
Not really, depends on how you look at it.
Both Master and Slave are synchronous, but for single cycle transfers the
slave has to drive in the same cycle as the master. If you want to you could
see this as asynchronous. But since the entire transfer is controlled by the
wishbone clock (or embodied by two rising clock edges) the transfer is
synchronous.
>
> 2) If the slave does not respond immediately on the STB signal, then
> wait states are inserted, and everything is delayed, but is it necessary
> that the address remains stable until the ACK signal, or is one clock
> enough?
The master must keep all signals in the same state, until the slave
acknowledges. I.e. the address must remain stable.
Richard
>
> I hope someone can give me the answer,
> thanks and regards,
> Aspoous
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores WISHBONE AMBA-AHB bridge ////
//// ////
//// Author: Richard Herveille ////
//// rherveille@opencores.org ////
//// www.opencores.org ////
//// ////
//// Known limitations: ////
//// - ACK, RTY & ERR are all treated as two cycle responses. ////
//// - Although a parameter, the data-width is currently fixed ////
//// to 32bits. ////
//// - CAB signal is only generated on incrementing bursts of ////
//// undefined length. ////
//// ////
//// TODO: ////
//// - Fix SEL signals, so data-width can be a true parameter. ////
//// - Make CAB generation smarter ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// rherveille@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: $
//
// $Date: $
// $Revision: $
// $Author: $
// $Locker: $
// $State: $
//
module ahb2wb_bridge(
hclk, hresetn, hsel, haddr, htrans, hburst, hsize, hwrite, hrdata, hwdata,
hready, hresp,
clk_o, rst_o, cyc_o, stb_o, cab_o, sel_o, adr_o, dat_i, dat_o, we_o,
ack_i, rty_i, err_i
);
///////////////////
// parameters
//
parameter awidth = 32;
parameter dwidth = 32;
////////////////////
// inputs & outputs
//
// AMBA APB interface
input hclk;
input hresetn;
input hsel;
input [awidth-1:0] haddr;
input [1:0] htrans; // 00 idle
// 01 busy
// 10 non-seq
// 11 seq
input [2:0] hburst; // 000 SINGLE single transfer
// 001 INCR Incrementing burst
// 010 WRAP4 4-beat wrapping burst
// 011 INCR4 4-beat incrementing burst
// 100 WRAP8 8-beat wrapping burst
// 101 INCR8 8-beat incrementing burst
// 110 WRAP16 16-beat wrapping burst
// 111 INCR16 16-beat incrementing burst
input [2:0] hsize; // 000 8bit
// 001 16bit
// 010 32bit
// 011 64bit
// 100 128bit
// 101 256bit
// 110 512bit
// 111 1024bit
input hwrite;
output [dwidth-1:0] hrdata;
input [dwidth-1:0] hwdata;
output hready;
output [1:0] hresp; // 00 OKAY
// 01 ERROR
// 10 RETRY
// 11 SPLIT
// WISHBONE interface
output clk_o;
output rst_o;
output cyc_o;
output stb_o;
output cab_o;
output [dwidth/8:1] sel_o;
output [awidth-1:0] adr_o;
output [dwidth-1:0] dat_o;
input [dwidth-1:0] dat_i;
output we_o;
input ack_i;
input rty_i; // simply ignore rty signal
input err_i;
//////////////////////////
// constant declarations
//
parameter HRESP_OKAY = 2'b00;
parameter HRESP_ERROR = 2'b01;
parameter HRESP_RETRY = 2'b10;
parameter HRESP_SPLIT = 2'b11;
//////////////////
// functions
//
//////////////////
// Module body
//
wire ihready;
//
// AMBA AHB bus cycles
//
// 1) idle
// 2) address (1 cycle) -> present address, control
// 3) data
//
// data-cycle and next address-cycle overlap
//
// WISHBONE SIGNALS
//
assign clk_o = hclk;
assign rst_o = ~hresetn;
assign dat_o = pwdata;
// generate the wishbone control signals
always @(posedge clk)
if (hready)
begin
cyc_o <= #1 hsel;
stb_o <= #1 hsel & htrans[1] & ~ihready; // assert stb when SEQ or NON_SEQ
cab_o <= #1 htrans[1] & htrans[0] & !hburst[2] & !hburst[1] & hburst[0];
we_o <= #1 pwrite;
adr_o <= #1 haddr;
end
// generate SEL signals
always @(posedge clk)
case (hsize)
3'b000:
endcase
//
// AMBA-AHB signals
//
assign prdata = dat_i;
assign hready = hsel & (ack_i | rty_i | err_i);
// generate the transfer response signals
assign ihready = ack_i | rty_i | err_i;
always @(posedge clk)
hready <= #1 ihready;
always @(ihready or hready or rty_i or err_i)
begin
hresp = HRESP_OKAY;
if ( (ihready | hready) & (rty_i | err_i) )
if (rty_i)
hresp = HRESP_RETRY;
else
hresp = HRESP_ERROR;
end
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores AMBA-APB Wishbone bridge ////
//// ////
//// Author: Richard Herveille ////
//// rherveille@opencores.org ////
//// www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// rherveille@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: $
//
// $Date: $
// $Revision: $
// $Author: $
// $Locker: $
// $State: $
//
module wb2apb_bridge(
clk_i, rst_i, cyc_i, stb_i, adr_i, dat_i, dat_o, we_i, ack_o, rty_o, err_o,
pclk, presetn, paddr, psel, penable, pwrite, prdata, pwdata
);
//
// parameters
//
parameter dwidth = 32;
parameter awidth = 32;
//
// inputs & outputs
//
// WISHBONE interface
input clk_i;
input rst_i;
input cyc_i;
input stb_i;
input [awidth-1:0] adr_i;
input [dwidth-1:0] dat_i;
output [dwidth-1:0] dat_o;
input we_i;
output ack_o;
output rty_o;
output err_o;
// AMBA APB interface
output pclk;
output presetn;
output [awidth-1:0] paddr;
output psel;
output penable;
output pwrite;
input [dwidth-1:0] prdata;
output [dwidth-1:0] pwdata;
//
// Module body
//
reg penable;
//
// AMBA APB bus cycles
//
// 1) idle
// 2) setup (1 cycle) -> present address, write, select etc
// 3) enable (1 cycle) -> done, goto idle or setup
//
// This means an APB transfer always takes 2 cycles, there are no
// wait states.
// start assigning the easy stuff
assign pclk = clk_i;
assign presetn = ~rst_i;
assign paddr = adr_i;
assign psel = cyc_i & stb_i;
assign pwrite = we_i;
assign pwdata = dat_i;
// create the enable signal
always @(posedge clk_i)
penable <= #1 psel & ~penable;
// assign the wishbone outputs
assign dat_o = prdata;
assign ack_o = penable;
assign rty_o = 1'b0; // no retries
assign err_o = 1'b0; // no bus-errors
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores AMBA-AHB Wishbone bridge ////
//// NOT FINISHED ////
//// Author: Richard Herveille ////
//// rherveille@opencores.org ////
//// www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// rherveille@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: $
//
// $Date: $
// $Revision: $
// $Author: $
// $Locker: $
// $State: $
//
module wb2ahb_bridge(
clk_i, rst_i, cyc_i, stb_i, adr_i, dat_i, dat_o, we_i, ack_o, rty_o, err_o,
pclk, presetn, paddr, psel, penable, pwrite, prdata, pwdata
);
//
// parameters
//
parameter dwidth = 32;
parameter awidth = 32;
//
// inputs & outputs
//
// WISHBONE interface
input clk_i;
input rst_i;
input cyc_i;
input stb_i;
input [awidth-1:0] adr_i;
input [dwidth-1:0] dat_i;
output [dwidth-1:0] dat_o;
input we_i;
output ack_o;
output rty_o;
output err_o;
// AMBA APB interface
output pclk;
output presetn;
output [awidth-1:0] paddr;
output psel;
output penable;
output pwrite;
input [dwidth-1:0] prdata;
output [dwidth-1:0] pwdata;
//
// Module body
//
reg penable;
//
// AMBA APB bus cycles
//
// 1) idle
// 2) setup (1 cycle) -> present address, write, select etc
// 3) enable (1 cycle) -> done, goto idle or setup
//
// This means an APB transfer always takes 2 cycles, there are no
// wait states.
// start assigning the easy stuff
assign pclk = clk_i;
assign presetn = ~rst_i;
assign paddr = adr_i;
assign psel = cyc_i & stb_i;
assign pwrite = we_i;
assign pwdata = dat_i;
// create the enable signal
always @(posedge clk_i)
penable <= #1 psel & ~penable;
// assign the wishbone outputs
assign dat_o = prdata;
assign ack_o = penable;
assign rty_o = 1'b0; // no retries
assign err_o = 1'b0; // no bus-errors
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores WISHBONE AMBA-APB bridge ////
//// ////
//// Author: Richard Herveille ////
//// rherveille@opencores.org ////
//// www.opencores.org ////
//// ////
//// ////
//// Known limitations: ////
//// - AMBA-APB doesn't allow wait states, therefore a WISHBONE ////
//// slave with more than 1 wait state can not be connected to ////
//// the AMBA-APB bus. ////
//// - AMBA-APB doesn't provide any retry or error signals, ////
//// therefore the WISBONE rty signal is ignored and the err ////
//// signal indicates a normal transfer done. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Richard Herveille ////
//// rherveille@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: $
//
// $Date: $
// $Revision: $
// $Author: $
// $Locker: $
// $State: $
//
module apb2wb_bridge(
pclk, presetn, paddr, psel, penable, pwrite, prdata, pwdata,
clk_o, rst_o, cyc_o, stb_o, adr_o, dat_i, dat_o, we_o, ack_i, rty_i, err_i
);
//
// parameters
//
parameter dwidth = 32;
parameter awidth = 32;
//
// inputs & outputs
//
// AMBA APB interface
input pclk;
input presetn;
input [awidth-1:0] paddr;
input psel;
input penable; // ignore penable
input pwrite;
output [dwidth-1:0] prdata;
input [dwidth-1:0] pwdata;
// WISHBONE interface
output clk_o;
output rst_o;
output cyc_o;
output stb_o;
output [awidth-1:0] adr_o;
output [dwidth-1:0] dat_o;
input [dwidth-1:0] dat_i;
output we_o;
input ack_i;
input rty_i; // simply ignore rty signal
input err_i;
//
// Module body
//
//
// AMBA APB bus cycles
//
// 1) idle
// 2) setup (1 cycle) -> present address, write, select etc
// 3) enable (1 cycle) -> done, goto idle or setup
//
// This means an APB transfer always takes 2 cycles, there are no
// wait states.
//
// CAUTION:
// The above described APB interface limits the use of this bridge.
// This bridge can (currently) only be used by WISHBONE slaves with
// a zero or one cycle acknowledge delay. I.e. zero or one wait state.
/*
TODO
Fix WISHBONE wait states
Fix WISHBONE err signal
*/
// start assigning the easy stuff
assign clk_o = pclk;
assign rst_o = ~presetn;
assign adr_o = paddr;
assign cyc_o = psel;
assign stb_o = psel & !(ack_i | err_i);
assign we_o = pwrite;
assign dat_o = pwdata;
// assign the AMBA-APB outputs
assign prdata = dat_i;
endmodule