[oc] FPGA failure analysis

[esmailc <esmailc@gwu.edu>]

Dear Freinds,
I am relatively new to this group and i was hoping you would help me out in a 
topic i am researching. I am currently researching the reliability and failure 
modes of FPGAs for my current MS thesis. I was hoping that you people could 
give me a little feedback as to your experiences when dealing with FPGAs, 
things like have you guys used any circuit redundancy in your designs, or any 
built in self test mechanisms for your designs when implimenting them on the 
FPGAs.
Hoping to get a favorable response,
Esmail Chitalwala.

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml