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Re: [oc] To Jason

To: cores@opencores.org
Subject: Re: [oc] To Jason
From: tom st denis <tomstdenis@yahoo.com>
Date: Sun, 7 Jul 2002 07:09:39 -0700 (PDT)
In-Reply-To: <20020707134756.1309.qmail@web12705.mail.yahoo.com>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org

--- jae lim <jlim0011@yahoo.com> wrote:
> 
> Hello Jason 

Hello dorks.

I want off this list.  I sent an unscribe message.

Fuck y'all very much.

Tom

> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
> 
> Thank you very much for your input!
> 
> 
> > A better approach might be to design the pipeline
> > with various points at which the execution could be
> > registered and turn them on or off using synthesis 
> > directives and GENERICS.Thus for different FPGA 
> > architectures and synthesis tools the code could be 
> > optimized to have the best performance.
> 
> 
> How can I design the pipeline at different points at
> which the execution could be registered? What is
> GENERICS?
>  
> And also, about the control logic, could you explain
> to me in more detail? I am really new to this area:--(
> 
> THanks again and have a nice weekend.
> 
> Xia 
> 
> __________________________________________________
> Do You Yahoo!?
> Sign up for SBC Yahoo! Dial - First Month Free
> http://sbc.yahoo.com
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
vv

__________________________________________________
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