Re: [oc] FPGA- Constrains

[scartic@ixiacom.com]

>From your mail it seems to me like you want to try the design using
FPGAs as a proof of concept. If that's the case, it may be possible
to run the entire design at a reduced clock rate. If the design does not
depend on asynchronous delays to function you might be able to test
the complete design at some convenient frequency - 10mhz for example,
where you are not concerned with timing issues anymore.

If you want to constrain the design, you can use synopsys directives
to constrain synthesis. you can also use FROM TO constraints in
the UCF file.

I believe you can find constraints guide documents in the xilinx web site 
download section..


Sanjay




----- Original Message ----- 
From: "R. Ramakrishna" <rayaprolu_rk@y... > 
To: cores@o...  
rayaprolu_rk@y...  
Date: Sat, 19 Oct 2002 03:25:26 -0700 (PDT) 
Subject: [oc] FPGA- Constrains 

> Hi All, 
> 
> I mailed earlier to the cores list about my problem and asked for 
> help but unfortunately got no replies. So I am trying to put my 
> question in a little different way::: 
> 
> Firstly, I would like to introduce myself. I completed my Masters 
> in Engg( spl in Digital Systems) from Osmaina University, 
> Hyderabad, India very recently and joined a pvt firm as a trainee. 
> 
> I am working on FPGA-Validation of a fairly large design, before it 
> goes for the fab. My job is to port the design onto FPGA (VirtexE 
> device of Xilinx) for this purpose. The problem I am facing is that 
> the frequency of operation that I am able to achieve is very less, 
> and the design being large, I cannot change my design for the FPGA. 
> I need to put Constraints thru UCF and make it run at as high a 
> frequency as the tool can give me. I am working with FPGA express 
> for synthesis and ISE 4.1i for PNR. 
> 
> I am trying to port the Synopsys's DC directives like " 
> set_false_path", "set multicycle_path", set dont_touch" and any 
> other attributes that would help me in reducing the critical path 
> delay in my design. [and constrain the net delay, ofcourse] 
> 
> Can any one of you kindly point me to some relavant documentation 
> on approach to applying constraints on a design, in general and 
> similar documentation on FPGA constraints? 
> 
> Please correct me if my approach is wrong. Please let me know if I 
> am not clear in any aspect. 
> 
> Thank you. 
> 
> Rayaprolu 
> 
> 
> 
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> 
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