RE: [oc] Design Question

[Victor Snesarev <vnsnes@yahoo.com>]

I used Icarus Verilog for a little while under Linux. 
It supports mostly Xilinx FPGAs for synthesis, but,
from the sound of the FAQ, may be persuaded to
generate an EDIF.  Binaries for other operating
systems exist.

http://icarus.com/eda/verilog/index.html


-Victor
--- Rudolf Usselmann <rudi@asics.ws> wrote:
> On Mon, 2003-02-03 at 20:44, Ho, Wen Jei x4297
> wrote:
> > How do I get those "free (beer) ones" ?
> > 
> > Thanks, Wen
> > 
> 
> Very good question !
> 
> I personally know of only one 'free' synthesis tool.
> It's actually a collection of tools, informally
> known
> as the "Berkley Tools". They included an equation
> compiler
> (optimizer) and a FSM compiler, and I believe a few
> other tools. They where all command line Unix tools.
> They would take "high level equations" and optimize
> them,
> and then later you could convert them to a net list.
> 
> If I remember correctly Synopsys used them as a
> starting
> point for it's Design Compiler.
> We actually used these tools at SUN when I did my
> first
> chip (there was no Synopsys at that time - LSI Logic
> had
> some proprietary tools - LSI Logic was kind of the
> leader
> at that time).
> 
> Would be interesting to find out what ever happened
> to
> these tools, if somebody has the time to search the
> net,
> please post the results !
> 
> Cheers !
> 
> rudi
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