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[oc] PLL vs DLL



or the full control on clock delays & clock phases,which 
architecture is preferrable PLL or DLL.i know tht each one has its 
advantages,but both altera & Xilinx claims tht their PLL(in 
stratix) & DLL(in virtex or spartan-IIE) architecture has an edge 
over other.getting large multiples of frequencies in PLL is also 
an added advantage.where i can find the comparison between the 
two.

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