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Re: [oc] FPGA BOARD Considerations
At 08:33 27/03/2003 +1100, you wrote:
>On Wed, Mar 26, 2003 at 09:05:46PM +0100, H�ctor Or�n Mart�nez wrote:
> > for your experience to do with memory to program SRAM FPGA ? and what
> do you
> > think of it being modular and having for that a maximum frec penalty?
>
>Why have a resident config scheme at all?
>Use a host pc to download. It has to be there occasionally to get the
>config into the programming device.
>Go straight in to the fpga using jtag.
>
>It is a shock to discover the config device is comparable in cost to
>the fpga.
>
>if there is a cpu with flash elsewhere in the project,
>using that makes sense. As long as the fpga is not essential to the
>cpu boot.
>
>A cpld and a standard flash can sometimes also be cost effective.
>john
We are using low cost standard Flash device (29F080) to store Xilinx
Spartan II Device bistreams. The loading process into the FPGA is aided by
and a low cost CPLD, basically to generate FLASH addresses and loading
signals. Also the cpld is used into the flash write process. In this case
the information is received from the pc by an external microntroller (8-PIC
with USART) and written to the FLASH. Using this scheme also different
bitstreams for the target can be stored into the flash. With Xilinx devices
the configuration port to perform parallel loading is called SelectMap,
probably with Altera you will have something similar. This solution is
really cheap.
References :
Chris Dunlap, Tom Fischaber, "Configuring Xilinx FPGAs Using an XC9500
CPLD and Parallel PROM," Xilinx Application Notes, n. , July, 2000.
Carl Carmichael, Kim Goldblatt, "Configuring Spartan-II FPGAs from
Parallel EPROMs," Xilinx Application Notes, n. , December, 1999.
Armando
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Armando Astarloa Cuéllar - Universidad del Pais Vasco UPV/EHU
Tecnología Electrónica
Departamento de Electrónica y Telecomunicaciones
Escuela Superior de Ingenieros - Email: jtpascua@bi.ehu.es
Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04
48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59
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