[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[oc] VHDL Problem

To: cores@opencores.org
Subject: [oc] VHDL Problem
From: "Matija Habek" <mhabek@net.hr>
Date: Wed, 9 Jul 2003 23:55:00 +0200
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org

Can I simulate a pull-up resistor in VHDL using Graphic Editor and how?

--
Besplatni e-mail - http://webmail.iskon.hr/
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml

Follow-Ups:
- Re: [oc] VHDL Problem
  - From: Héctor Orón Martínez <hecormar@teleco.upv.es>

Prev by Date: Re: [oc] CAN core in VHDL
Next by Date: [oc] How to make SRAM Library Parameterized Magafunction
Prev by thread: [oc] How to make SRAM Library Parameterized Magafunction
Next by thread: Re: [oc] VHDL Problem
Index(es):
- Date
- Thread