hi,
here is 386 behavioural model
http://tech-www.informatik.uni-hamburg.de/vhdl/models/i80386/i80386.vhd
Deepu
-----Original Message-----
From: Rudolf Usselmann [mailto:rudi@asics.ws]
Sent: Tuesday, July 29, 2003 3:29 PM
To: cores@opencores.org
Subject: Re: [oc] x86 IP Core
On Tue, 2003-07-29 at 17:13, watchman@ludd.luth.se wrote:
> Aloha!
>
> From: antti@c...
>
> > x86 Core options:
> >
> > 1) cycle accurate clone (real headache)
> > 2) classical microcode engine (boring)
> > 3) microcode engine that can reload on the fly - you could achieve
> > even full pentium 6 support because new microcodes are loadable
> > (well speed penalty)
>
> These are important issues. Rudi, do you need to have a cycle accurate
> core, or just instruction order accurate? Also, programmable
> decode/translate might be something to consider. Eats memory but will
> buy you flexibility including incremental development.
At this point I was just trying to se *what is available
for free*. I'd like to find a FREE, like FREE Beer IP Core !
If it comes with it's own beer even better !
I don't care to much about the bus, but I hope to find
something that is instruction order/result accurate.
Trying to find a free solution I can't be to choosy. If
I decide I have to write it myself, I will carefully
evaluate those questions and probably many more.
If I find a free IP core, it might be cheaper/easier to
adjust my application, or perhaps the IP.
> /Joachim Strombergson - ASIC hacker at large (as in roaming free)
You supposed to relax on vacation, not hack ASICs ! ;*)
Regards,
rudi
--------------------------------------------------------
www.asics.ws --- Solutions for your ASIC/FPGA needs ---
----------------- FPGAs * Full Custom ICs * IP Cores ---
FREE IP Cores --> http://www.asics.ws/ <-- FREE IP Cores
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml