[cvs-checkins] mem_ctrl/ ench/verilog/test_bench_top.v ench/v ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	mem_ctrl
Changes by:	rudi	01/08/10 10:16:22

Modified files:
	bench/verilog  : test_bench_top.v tests.v 
	doc            : mc_doc.pdf 
	rtl/verilog    : mc_adr_sel.v mc_cs_rf.v mc_defines.v mc_dp.v 
	                 mc_obct_top.v mc_rf.v mc_timing.v mc_top.v 
	                 mc_wb_if.v 
	sim/rtl_sim/bin: Makefile 

Log message:
	- Changed IO names to be more clear.
	- Uniquifyed define names to be core specific.
	- Removed "Refresh Early" configuration

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