[cvs-checkins] wb_dma/ ench/verilog/test_bench_top.v ench/ver ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	wb_dma
Changes by:	rudi	01/08/15 07:40:30

Modified files:
	bench/verilog  : test_bench_top.v tests.v 
	doc            : dma_doc.pdf 
	rtl/verilog    : wb_dma_ch_pri_enc.v wb_dma_ch_rf.v 
	                 wb_dma_ch_sel.v wb_dma_de.v wb_dma_defines.v 
	                 wb_dma_pri_enc_sub.v wb_dma_rf.v wb_dma_top.v 
	                 wb_dma_wb_slv.v 
	sim/rtl_sim/bin: Makefile 

Log message:
	- Changed IO names to be more clear.
	- Uniquifyed define names to be core specific.
	- Added Section 3.10, describing DMA restart.

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