[cvs-checkins] vga_lcd/ ench/verilog/sync_check.v ench/verilo ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	vga_lcd
Changes by:	rudi	01/08/21 07:42:33

Added files:
	bench/verilog  : sync_check.v test_bench_top.v tests.v 
	                 wb_mast_model.v wb_model_defines.v 
	                 wb_slv_model.v 
	doc            : vga_core.pdf 
	doc/src        : vga_core.doc 
	rtl/verilog    : ro_cnt.v timescale.v ud_cnt.v vga_colproc.v 
	                 vga_csm_pb.v vga_dpm.v vga_fifo.v vga_fifo_dc.v 
	                 vga_fpga_top.v vga_fpga_vga_and_clut.v 
	                 vga_pgen.v vga_tgen.v vga_top.v 
	                 vga_vga_and_clut.v vga_vtim.v vga_wb_master.v 
	                 vga_wb_slave.v 
	rtl/vhdl       : colproc.vhd counter.vhd csm_pb.vhd dpm.vhd 
	                 fifo.vhd fifo_dc.vhd pgen.vhd tgen.vhd vga.vhd 
	                 vga_and_clut.vhd vga_and_clut_tstbench.vhd 
	                 vtim.vhd wb_master.vhd wb_slave.vhd 
	sim/rtl_sim/bin: Makefile 
	syn/bin        : comp.dc design_spec.dc lib_spec.dc read.dc 

Log message:
	- Changed Directory Structure
	- Added verilog Source Code
	- Changed IO pin names and defines statements

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