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[cvs-checkins] Import

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] Import
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Tue, 2 Oct 2001 17:37:10 +0200
Sender: owner-cvs-checkins@opencores.org
CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	oc	01/10/02 17:37:10

Log message:
    New project directory structure
    
    Status:
    
    Vendor Tag:	mihad
    Release Tags:	initial
    
    U pci/doc/pci_specification.pdf
    U pci/apps/crt/rtl/verilog/ssvga_wbs_if.v
    U pci/apps/crt/rtl/verilog/ssvga_defines.v
    U pci/apps/crt/rtl/verilog/ssvga_fifo.v
    U pci/apps/crt/rtl/verilog/ssvga_top.v
    U pci/apps/crt/rtl/verilog/ssvga_wbm_if.v
    U pci/apps/crt/rtl/verilog/ssvga_crtc.v
    U pci/apps/crt/rtl/verilog/timescale.v
    U pci/apps/crt/rtl/verilog/top.v
    U pci/apps/crt/syn/ucf/pci_crt.ucf
    U pci/apps/crt/syn/exc/pci_crt.exc
    U pci/apps/crt/syn/out/bit/pci_crt.bit
    U pci/apps/crt/syn/out/verilog/crt_time_sim.v
    U pci/apps/crt/syn/out/verilog/crt_time_sim.v.bak
    U pci/apps/crt/syn/out/sdf/crt_time_sim.sdf
    U pci/rtl/verilog/wb_slave_unit.v
    U pci/rtl/verilog/cbe_en_crit.v
    U pci/rtl/verilog/conf_cyc_addr_dec.v
    U pci/rtl/verilog/conf_space.v
    U pci/rtl/verilog/constants.v
    U pci/rtl/verilog/cur_out_reg.v
    U pci/rtl/verilog/decoder.v
    U pci/rtl/verilog/delayed_sync.v
    U pci/rtl/verilog/delayed_write_reg.v
    U pci/rtl/verilog/dp_async_ram.v
    U pci/rtl/verilog/dp_sram.v
    U pci/rtl/verilog/fifo_control.v
    U pci/rtl/verilog/frame_crit.v
    U pci/rtl/verilog/frame_en_crit.v
    U pci/rtl/verilog/frame_load_crit.v
    U pci/rtl/verilog/io_mux_en_mult.v
    U pci/rtl/verilog/io_mux_load_mux.v
    U pci/rtl/verilog/irdy_out_crit.v
    U pci/rtl/verilog/mas_ad_en_crit.v
    U pci/rtl/verilog/mas_ch_state_crit.v
    U pci/rtl/verilog/mas_load_next_crit.v
    U pci/rtl/verilog/out_reg.v
    U pci/rtl/verilog/par_cbe_crit.v
    U pci/rtl/verilog/par_crit.v
    U pci/rtl/verilog/pci_bridge32.v
    U pci/rtl/verilog/pci_decoder.v
    U pci/rtl/verilog/pci_in_reg.v
    U pci/rtl/verilog/pci_io_mux.v
    U pci/rtl/verilog/pci_master32_sm.v
    U pci/rtl/verilog/pci_master32_sm_if.v
    U pci/rtl/verilog/pci_parity_check.v
    U pci/rtl/verilog/pci_target_unit.v
    U pci/rtl/verilog/pci_target32_ad_en_crit.v
    U pci/rtl/verilog/pci_target32_clk_en.v
    U pci/rtl/verilog/pci_target32_ctrl_en_crit.v
    U pci/rtl/verilog/pci_target32_devs_crit.v
    U pci/rtl/verilog/pci_target32_interface.v
    U pci/rtl/verilog/pci_target32_load_crit.v
    U pci/rtl/verilog/top.v
    U pci/rtl/verilog/pci_target32_sm.v
    U pci/rtl/verilog/pci_target32_stop_crit.v
    U pci/rtl/verilog/pci_target32_trdy_crit.v
    U pci/rtl/verilog/pciw_fifo_control.v
    U pci/rtl/verilog/pciw_pcir_fifos.v
    U pci/rtl/verilog/perr_crit.v
    U pci/rtl/verilog/perr_en_crit.v
    U pci/rtl/verilog/serr_crit.v
    U pci/rtl/verilog/serr_en_crit.v
    U pci/rtl/verilog/synchronizer_flop.v
    U pci/rtl/verilog/wb_addr_mux.v
    U pci/rtl/verilog/wb_master.v
    U pci/rtl/verilog/wb_slave.v
    U pci/rtl/verilog/bus_commands.v
    U pci/rtl/verilog/wbr_fifo_control.v
    U pci/rtl/verilog/wbw_fifo_control.v
    U pci/rtl/verilog/wbw_wbr_fifos.v
    U pci/sw/driver/spartan_kint.h
    U pci/sw/driver/Makefile
    U pci/sw/driver/README.txt
    U pci/sw/driver/sdram_test
    U pci/sw/driver/sdram_test.c
    U pci/sw/driver/slide.c
    U pci/sw/driver/spartan_drv.c
    U pci/sw/driver/spartan_drv-2.2.o
    U pci/sw/driver/spartan_drv-2.4.o
    U pci/sw/driver/fb/XF86Config-fb
    U pci/sw/driver/fb/Makefile
    U pci/sw/driver/fb/spartan_fb.c
    U pci/sw/driver/fb/spartan_kint.h
    U pci/sw/driver/fb/startx
    U pci/old_stuff/constants.v
    U pci/old_stuff/bus_commands.v
    U pci/old_stuff/Decoder/tb_decoder.v
    U pci/old_stuff/Decoder/decoder.v
    U pci/old_stuff/Decoder/defines.v
    U pci/old_stuff/Decoder/readme.txt
    U pci/old_stuff/Decoder/tb_defines.v
    U pci/old_stuff/delayed_sync/delayed_sync.v
    U pci/old_stuff/delayed_sync/READ_ME.txt
    U pci/old_stuff/docs/pci_specification.pdf
    U pci/old_stuff/driver/sdram_test.c
    U pci/old_stuff/driver/Makefile
    U pci/old_stuff/driver/README.txt
    U pci/old_stuff/driver/sdram_test
    U pci/old_stuff/driver/slide.c
    U pci/old_stuff/driver/spartan_drv-2.2.o
    U pci/old_stuff/driver/spartan_drv-2.4.o
    U pci/old_stuff/driver/spartan_drv.c
    U pci/old_stuff/driver/spartan_kint.h
    U pci/old_stuff/driver/fb/XF86Config-fb
    U pci/old_stuff/driver/fb/Makefile
    U pci/old_stuff/driver/fb/spartan_fb.c
    U pci/old_stuff/driver/fb/spartan_kint.h
    U pci/old_stuff/driver/fb/startx
    U pci/old_stuff/FIFOs/pciw_pcir_fifos.v
    U pci/old_stuff/FIFOs/dp_async_ram.v
    U pci/old_stuff/FIFOs/dp_sram.v
    U pci/old_stuff/FIFOs/fifo_control.v
    U pci/old_stuff/FIFOs/pci_tb.v
    U pci/old_stuff/FIFOs/wbw_wbr_fifos.v
    U pci/old_stuff/FIFOs/read_me.pdf
    U pci/old_stuff/FIFOs/wb_tb.v
    U pci/old_stuff/pci_master32/pci_master32_sm.v
    U pci/old_stuff/pci_master32/pci_stat.v
    U pci/old_stuff/pci_target/pci_stat.v
    U pci/old_stuff/pci_target/pci_target32_sm.v
    U pci/old_stuff/wb_master/wb_master.v
    U pci/old_stuff/wb_slave/READ_ME.txt
    U pci/old_stuff/wb_slave/wb_slave.v
    U pci/old_stuff/wb_slave/delayed_write_reg.v
    U pci/old_stuff/wb_slave/test_bench/bus_commands.v
    U pci/old_stuff/wb_slave/test_bench/READ_ME.txt
    U pci/old_stuff/wb_slave/test_bench/delayed_write_reg.v
    U pci/old_stuff/wb_slave/test_bench/conf_space.v
    U pci/old_stuff/wb_slave/test_bench/constants.v
    U pci/old_stuff/wb_slave/test_bench/decoder.v
    U pci/old_stuff/wb_slave/test_bench/delayed_sync.v
    U pci/old_stuff/wb_slave/test_bench/dp_async_ram.v
    U pci/old_stuff/wb_slave/test_bench/dp_sram.v
    U pci/old_stuff/wb_slave/test_bench/fifo_control.v
    U pci/old_stuff/wb_slave/test_bench/test_bench.v
    U pci/old_stuff/wb_slave/test_bench/wb_bus_mon.v
    U pci/old_stuff/wb_slave/test_bench/wb_master32.v
    U pci/old_stuff/wb_slave/test_bench/wb_slave.v
    U pci/old_stuff/wb_slave/test_bench/wbw_wbr_fifos.v
    U pci/old_stuff/conf_space/conf_space.v
    
    No conflicts created by this import
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