[cvs-checkins] uart16550/rtl/verilog uart_receiver.v uart_regs.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/11/10 13:43:22

Modified files:
	rtl/verilog    : uart_receiver.v uart_regs.v 

Log message:
	Synthesis bugs fixed. Some other minor changes

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml