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[cvs-checkins] oc8051/syn/src/verilog oc8051_fpga_top.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] oc8051/syn/src/verilog oc8051_fpga_top.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Tue, 3 Sep 2002 14:22:08 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	oc8051
Changes by:	simont	02/09/03 14:22:08

Modified files:
	syn/src/verilog: oc8051_fpga_top.v 

Log message:
	added signals ack, stb and cyc
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