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[cvs-checkins] can/bench/verilog can_testbench.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] can/bench/verilog can_testbench.v
From: OpenCores CVS Agent <cvs@www.lampret.com>
Date: Wed, 5 Mar 2003 14:33:45 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	can
Changes by:	mohor	03/03/05 14:33:45

Modified files:
	bench/verilog  : can_testbench.v 

Log message:
	tx_o is now tristated signal. tx_oen and tx_o combined together.

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