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[cvs-checkins] spi/ ench/verilog/tb_spi_top.v oc/spi.pdf oc/s ...
CVSROOT: /home/oc/cvs
Module name: spi
Changes by: oc 03/04/15 16:11:56
Modified files:
bench/verilog : tb_spi_top.v
doc : spi.pdf
doc/src : spi.doc
rtl/verilog : spi_clgen.v spi_defines.v spi_shift.v spi_top.v
Log message:
Support for 128 bits character length added. Zero value divider bug fixed.
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