[ethmac] some improvement

[Mahmud Galela <mgalela@vlsi.itb.ac.id>]

hi, sorry i'm late.
thank you Illan for your questions, we made some changes and hope that the
diagram can help us to make some discussions.

preamble has patern as 10101010 per byte (for 7 bytes) and SFD has
patern as 10101011. if SFD detector find the 1-1, bits after it will be
written in receive buffer (work as small fifo). if SFD detector find 0-0,
there must be an error and the process terminated.
do we have to check that the paterns before 1-1 are 101010...or just
consider bit number 6 and 7(and also for 0-0) ?

is there another consideration when we move byte from receive buffer to
FIFO beside to synchronize with host system clock? (i mean the time
interval after the first byte written to receive buffer and it move to
FIFO)

i'm still trying to understand the details of the receive operations for
half and full duplex, as you can see the signals in diagrams are not
complete yet.