[ethmac] Interest in Ethernet Verilog or VHDL "system model"

["John Williams" <John.Williams@TI.com>]

Novan or Mahmud-
I am working on an ASIC that has an
Ethernet "switch" that interfaces to
two external PHYs across two MII ports.
The internal port interfaces to an
ARM7 MCU.  We are trying to find a
good system model that we can use
to control/analyze network activity
to verify our design.  Do you guys
know of any "open" solutions that
we could use?  Could we use the
modules that are specified on the
"opencores" site by hooking them
up as external devices to our MII
ports?

Any help you can offer would be
great!

Thanx in advance for your support.

Regards-John

~~~~~~~~~~~~~~~~~~~~~~~~~~~
John W. Williams
IP Phone Design Solutions
Texas Instruments, Inc.
(303) 651-5996 -- Office
(303) 378-7626 -- Mobile
john.williams@ti.com