[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[ethmac] about signal setup time

Hi,

In the verilog code of this ethernet ip core, I found that the
data of txd[3:0] vary at the positive edge of tx_clk. Then, there
is no setup time for the data. Why?


_____________________________________________
精彩演出，巨星云集  http://shopping.263.net/category16.htm
千种化妆品网上热卖  http://shopping.263.net/category04.htm