RE: [ethmac] Ethernet MAC Core questions.

["Illan Glasner" <iglasner@zumanetworks.com>]

Hi,

   I'm not sure as for the core exact status etc however few comment :

1. 
Back pressure have its own use however from system point of view back
pressure is dissaster and should not be used unless you realy really
need it. back pressure (and in this aspect also flow control) can reduce
the overall system bandwidth to be extremly low.

The point you don't loss packet in the majority of the cases is less
importent than the bandwidth you loss as most protocol have no problem
to "recover" from lost packet.

2.
Address resulotion to be done effectivly mean either use a large memorey
with some sort of hashing or a cam and I belive that this is not done
here. on the other hand as a "edge-MAC" you don't realy need to know the
"whole system" or even part of it all you need to know is your own MAC
(MAC's) and maybe multicast/broadcast depend on the application, so the
ARL is "reduce" to few address comperator which I belive this is what
done in this MAC.

IF you plan to use this mac in a bridge/router and not as "edge-MAC" you
will need for sure some sort of ARL to reduce wasted traffic.

have a nice day

   Illan

-----Original Message-----
From: Jacinto San Pablo [mailto:jacinto.sanpablo@s3group.com]
Sent: Tuesday, October 23, 2001 6:07 AM
To: ethmac@opencores.org
Subject: [ethmac] Ethernet MAC Core questions.



Dear Sir,

I've been told about the existence of OPENCORES organization. My
interest is basically in the MAC part of Ethernet networks, and it was a

pleasure to discover that you were working in the development of an
Ethernet MAC core.
After reading the Ethernet IP Core documentation and looking at the
code, I still have some shadowed points which I would like to ask you
for some clarifications on. Any kind of help will be much appreciated.

1) Does the Core implement Back Pressure in Half Duplex? If not, do you
not think it is useful ?
2) Does the Core recognize VLAN frames at reception or transmission ?
3) Have the Status Vectors for a transmitted or received frame been
implemented yet? What information do they provide?
4) Is the block going to implement Address Resolution Logic? If
not, how do you understand the whole system? I mean, is it planned to
implement the host as a microprocessor, which will check the addresses
and discard frames ?
5) I have seen that you are still working on the design. Do you know
roughly,
when each of the parts could be finished : documentation, code and
testbench ?

Thank you very much in advance.

Yours sincerely.


Jacinto San Pablo.

________________________________________________________________________

  Jacinto San Pablo García - IC Engineer - Communications Infrastructure

________________________________________________________________________


  Silicon & Software Systems (S3)  | Phone:     + 353-1-291-1357
  Whelan house                     | Reception: + 353-1-291-1000
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