RE: [ethmac] ??: RE: [ethmac] mii rx hold time

["Illan Glasner" <iglasner@zumanetworks.com>]

Hi,
 
   the answer is depend, meaning usualy you will have very little sqew
on your clock while longer delay on the signals and so you will likely
to have a 5-10n simple because of the clk->out of the FPGA plus rounting
etc and this should be sufficient for the hold. 
 
otherwise you might need to use the same "trick" the phy is doing or you
can let the clock from the phy enter your core not through dedicated
input and this will gain you for the trasmision about 2n which might be
enough tho' this will "heart" the recive side so I wouldn;t recommend
this to strongly.
 
have a nice day
 
   Illan
 


-----Original Message-----
From: zou.yixin@zte.com.cn [mailto:zou.yixin@zte.com.cn]
Sent: Tuesday, December 25, 2001 3:50 AM
To: ethmac@opencores.org
Subject: [ethmac] ??: RE: [ethmac] mii rx hold time



In some devices(phy),signals are outputed on the falling edge of the
reference clock to meet the 10 ns 
setup and hold time. Is that necessary? 
In this core,signals(txd,txen) are outputed on the rising edge of
tx_clk. 
Both ways are ok? 
Regards. 
      yxzhou 




	"Igor Mohor" <igorm@opencores.org> 
发件人： owner-ethmac@opencores.org 


2001-12-24 18:01 
请答复 给 ethmac 


        
        收件人：        <ethmac@opencores.org> 
        抄送：         
        主题：        RE: [ethmac] mii rx hold time


No, tx_clk and rx_clk are not synchronous. PHY generates both signals.
Yes, the hold time will meet. tx_clk and rx_clk 
are 25 Mhz (40 ns). 
  
Regards, 
    Igor 
  
  
-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On
Behalf Of zou.yixin@zte.com.cn
Sent: 24. december 2001 9:38
To: ethmac@opencores.org
Subject: [ethmac] mii rx hold time


hi, 
Merry Christmas! 

The following  is quoted from 802.3-2000E. 
"Figure 22–15 shows the timing relationship for the signals associated
with the receive data path at the MII 
connector. The timing is referenced to the rising edge of the RX_CLK.
The input setup time shall be a minimum 
of 10 ns and the input hold time shall be a minimum of 10 ns." 

"Figure 22–14 shows the timing relationship for the signals associated
with the transmit data path at the MII 
connector. The clock to output delay shall be a minimum of 0 ns and a
maximum of 25 ns." 

When i send data synchronouly with respect to TX_CLK rising edge,can the
10ns hold time met ?I assume the tx_clk and rx_clk are
synchronous(right?). How to avoid the hold time violation. 

 Thanks. 

                           yxzhou. 



--
To unsubscribe from ethmac mailing list please visit http://www.opencores.org/mailinglists.shtml