[ethmac] modelsim problems and BD-(mis)understanding

[Mathias Johansson <matti.johansson@telia.com>]

Hello all,

Today we finaly were ready to simulate our mixed-mode VHDL/Verilog-design, 
featuring the beloved Eth-core :-)

However, beeing somewhat of a newbe using Modelsim (5.3 or something), we 
got into some trouble. The whole project compiles fine, but when we choose 
"Load Design" and select our testbench, the tool complains about components 
not found. Primarily the Generic_Tpram wants 2 instances of RAMB4_s16_s16, 
this is fine, I know there are behavioural models of this somewhere in the 
synopsys or Xilinx libraries, suppose it's just a matter of digging out the 
right code and compile into work-library. (Or should I expect more troubles 
than that?)

But, a greater concern is the eth_wishbonedma.v-file. It instantiates 
several components "eth_sync_clk1_clk2", which does not exist in our 
work-library. Is this also a standard component (from which library in that 
case?), or where can we find this model? I hope this is just a stupid newbe 
misstake, we'd really like to get going with our simulations. :-)

On another note while we´re at it: I don't fully understand the 
block-ram/BufferDescriptor buffer in the Eth-core. What exactly is stored 
there? Buffer Descriptors, right? Who writes them there, CPU or DMA core? 
Shouldn't BD's be in main memory together with packet data? Like this:
(Addrs 0x123456): [BD-1] 16 bytes;[PACKET1 DATA];.... [BD-n][PACKET-n DATA]

Or should we store ONLY packed data in system memory, and let CPU write the 
BD's to eth-core? Which adress is the "base address" of BD's?
If I've understood this alternative correctly: the DMA then reads the next 
BD from the eth-buffer as needed, right, but the buffer says data should be 
read from system ram?

Thanx Igor, for a core which seems very well done. We're looking forward to 
getting it to work :-)

Best regards,
Mathias & Torbjörn

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