Re: [ethmac] Internal DMA & Buffer Descriptors

[kempaj@yahoo.com]

Thanks to those who replied! 

I will go check out that software example. For now I've coded my driver 
to #define the number of Rx BD's I wish to use, then I globally 
(statically) allocate 1500 bytes (max size of an ethernet frame) for each 
RX BD that I #define... after this, I write to each Rx BD in use, the 
starting address of each 1500-byte allocation. Hopefully this will work 
fine, and allow users to easily scale performance vs. system data 
memory usage.

- Jesse Kempa


----- Original Message ----- 
From: "Damjan Lampret" <lampret@o... > 
To: <ethmac@o... > 
Date: Wed, 7 Aug 2002 13:04:19 +0200 
Subject: Re: [ethmac] Internal DMA & Buffer Descriptors 

> 
> 
> Hello Everyone, 
> 
> there is a simple SoC example with the ethernet MAC and software 
> for it. 
> Software is a debug monitor that can send/receive frames. SoC and 
> software 
> are openrisc based. SoC is in opencores cvs under or1k/orp and 
> software is 
> under or1k/orpmon. There is also a version of orp_soc for Xess 
> XSV800 
> board - or1k/xess. 
> 
> regards, 
> Damjan 
> 
> ----- Original Message ----- 
> From: <simos@i... > 
> To: <kempaj@y... >; <ethmac@o... > 
> Sent: Wednesday, August 07, 2002 12:02 AM 
> Subject: Re: [ethmac] Internal DMA & Buffer Descriptors 
> 
> 
> > Hello Mr. Kempa. 
> > 
> > We are involved in a similar project, which is based on an 
> FLEX10KE100 
> > Altera FPGA. We have already developed the board and had it 
> fabricated. 
> > 
> > Since our projects look similar, we would like to state two 
> problems we 
> > are currently facing and ask you for any ideas/solutions. 
> > 
> > a) We are trying to contruct a loopback module that will 
> receive eth 
> > frames, store them and send them back to the media at once. In 
> the 
> > ethernet specification it is stated that when, for example, 
> the RISC 
> > wishes to send a frame, it puts it in the "memory". But where 
> is this 
> > memory? Is it inside the eth core, or should we contruct a 
> wishbone 
> > combatible one and put some additional logic that will be able 
> to address 
> > the eth core Buffers? 
> > 
> > b) We want to write a simple software that sends and receives 
> raw eth 
> > frames. Any simple idea of how to do this? 
> > 
> > Thank you very much in advance. Your help will be most 
> valuable. 
> > 
> > Simos Dimitrios, 
> > Nikolas Kokkalis 
> > {simos, kokkalis}@ics.forth.gr 
> > 
> > ----- Original Message ----- 
> > From: kempaj@y... 
> > To: ethmac@o... 
> > Date: Tue, 6 Aug 2002 19:25:54 -0100 
> > Subject: [ethmac] Internal DMA & Buffer Descriptors 
> > 
> > > 
> > > 
> > > Hello, 
> > > 
> > > I am wondering if anyone can be of assistance in a 
> clarification. I 
> > > recently (just a couple weeks ago) downloaded Igor's 
> latest 
> > > revision of 
> > > the MAC core, and am working on integrating it for use 
> with a 
> > > soft-core 
> > > CPU (nios) as a research project. 
> > > 
> > > I've managed to sucessfully tie together the core to my 
> logic, and 
> > > poke 
> > > registers around as well. The next step was to tackle 
> software 
> > > design, 
> > > and I am about 90% done with a low-level driver that 
> interfaces the 
> > > MAC core to my TCP/IP stack. The last step will, of 
> course, be to 
> > > implement any MII commands for the PHY, but I'm waiting 
> for a board 
> > > we design with a phy on it to come back from fab. 
> > > 
> > > Anyways here is the problem: I understand (I think) how 
> BDs work 
> > > for 
> > > transmission with internal DMA. I set all the control 
> bits as I 
> > > wish, set 
> > > the length, and set a pointer to the address in data 
> memory where 
> > > my 
> > > TCP/IP stack has assembled a packet to send (Wishbone DMA 
> inside 
> > of 
> > > Igor's core masters this memory along with my CPU). I 
> give the GO 
> > > command and the frame is transmitted - this is all clear 
> to me. 
> > > 
> > > What is not clear to me is BD operation when receiving 
> frames. In 
> > > the 
> > > Ethernet IP Core Specification PDF document, page 29 
> (frame 
> > > reception) 
> > > states: "The Ethernet IP Core reads the Rx BD...After the 
> whole 
> > > frame 
> > > has been received and stored to the memory, the receive 
> status and 
> > > the pointer to memory storing the data are written to the 
> BD". 
> > > 
> > > Herein lies my confusion: How does the MAC core and/or 
> DMA know 
> > > where to store the received data???? I thought that the 
> memory 
> > > allocation for the MAC core was only for control 
> registers and 
> > > buffer 
> > > descriptors, so this would imply that the DMA portion of 
> the MAC 
> > > core "knows" where to store incoming frames into 
> memory... ideally 
> > > I'd 
> > > like to control the DMA destination from my CPU - i.e. - 
> write a 
> > > pointer 
> > > of my choice to the Rx BD's frame pointer, and have DMA 
> store the 
> > > frame memory starting at that address whenever a frame 
> comes in. 
> > > 
> > > This way, my software architecture can very easily be 
> designed to 
> > > scale 
> > > the number of buffer descriptors in use, and statically 
> allocate 
> > > 1,500 
> > > bytes (per ethernet packet) of memory for each 
> descriptor. 
> > > 
> > > If anyone can clarify the above operation of the Rx BDs, 
> I would be 
> > > very 
> > > greatful! 
> > > 
> > > Thank you, 
> > > 
> > > Jesse Kempa 
> > > 
> > 
> > 
> 
--
To unsubscribe from ethmac mailing list please visit http://www.opencores.org/mailinglists.shtml