[ethmac] FIFO width generic didnt work (eth_defines.v)

[Torbjörn Aronsson <e96ta@NOSPAM_efd.lth.se>]

Hi Igor,

we've synthesized our ethernet module, but found that two "wires" in eth_wishbone, connected to the fifo-modules, used hardcoded default widths instead of using the values supplied in eth_defines.v.
This created some problems in synthesis when we played around with different FIFO-depths (signals of different widths).

In our version of eth_wishbone.v (1.37):

line 1001:
   wire [4:0] txfifo_cnt
should read:
   wire [`TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt

and line 1923:
   wire [4:0] rxfifo_cnt
should read:
   wire [`RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt

hope this helps...
Torbjörn & Mathias
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