RE: [ethmac] operator precedence

["Igor Mohor" <igorm@opencores.org>]

Sorry, 

but at the moment I don't have time to go through all files and add
parentheses as you suggested.

Regards,
	Igor



> -----Original Message-----
> From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On
> Behalf Of zjli@technologist.com
> Sent: 11. oktober 2002 21:28
> To: zjli@technologist.com; ethmac@opencores.org
> Subject: Re: [ethmac] operator precedence
> 
> 
> The precedence of unary "|" is not completely clear in IEEE 1364-1995 
> and IEEE 1364-2001. Under the section title "Binary operator 
> precedence", "|" is listed only once while "+" and "-" are listed 
> as binary 
> and unary separately. I took this "|" as both unary and binary 
> because "|" and "~|" are listed as having the same precedence, 
> and "~|" is always unary.
> 
> The draft LRM for the future Verilog standard clearly listed that 
> all unary 
> operators have higher precedence than all binary operators.
> 
> It is a good idea to add parentheses in such cases.
> 
> ----- Original Message ----- 
> From: zjli@t...  
> To: ethmac@o...  
> Date: Wed, 9 Oct 2002 22:40:41 -0100 
> Subject: [ethmac] operator precedence 
> 
> > 
> > 
> > In eth_receivecontrol.v, "if(|PauseTimer[15:0] & RxFlow)" is 
> > currently 
> > used for computing Divider2. Apparently, it meant "if((|PauseTimer 
> > [15:0]) & RxFlow)" but it could mean "if(|(PauseTimer[15:0] 
> > & RxFlow))" 
> > according to both IEEE 1364-1995 and IEEE 1364-2001. 
> > 
> > I am curious what tools did not agree with my interpretation of 
> > IEEE 
> > standards. 
> > 
> > Thanks, 
> > Jeff 
> > 
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