[ethmac] Some questions...

[nikos@microlab.ntua.gr]

Dear all,

I am trying to check the simulation of the MAC using MSim...Everything 
is running ok, but i can't change the number of test... I think the 
variable test_num is responsible for it but all i get at the Wave Window 
is test 20... How can I change it??

I am also thinking of replacing the Wishbone Interface with a proprietary 
one of my own...This implies eliminating the buffer descriptor logic. All I 
need is the Rx and Tx FIFO to buffer the reception and transmission 
data paths plus the control signaling. Any comments about that?

I am sorry if I ask silly things but I am not so familiar to VERILOG...

Thank you for your time...

PS.: Igor..Excellent work...

--
To unsubscribe from ethmac mailing list please visit http://www.opencores.org/mailinglists.shtml