[ethmac] rx_clk in loopback

["Igor Mohor" <igorm@opencores.org>]

Hi, Guys.

I got a bug report that in loopback many packets are received with a CRC
error.
This happens because data and control signals are loopbacked while rx_clk
isn't.

So loopback signals are not synchronous with the rx_clk any more.

One solution would be to do something like
   rx_clk = loop_back ? tx_clk_pin : rx_clk_pin:

In this case we have a gated clock which I believe is a bad solution.

Another solution would be to somehow synchronize data and control signals to
tx_clk.
when in loopback.


Any good idea?

Solution must be good for both, FPGA and ASIC.

Regards,
	Igor



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