[ethmac] problem using xilinx vertex2 with ETH_XILINX_RAMB4 option

[icyman@catholic.or.kr]

I am verifying ethmac in xilinx vertex2..

At frist.. it looked wrong rx & tx operation.. but functional simulation is 
OK..

Some broken packet is received and transmitted.

But MAC address is no problem in transmitted packet.

So I assumed "Ah.. there is some broblem in rx & tx buffer.."

I used the option(below) in eth_defines.v file..

// Ethernet implemented in Xilinx Chips
// `define ETH_FIFO_XILINX    
 `define ETH_XILINX_RAMB4 

I think it makes some trouble in xilinx vertex2 at P&R time..

It looks good after I do not use either of them.. 

Be careful.. functional simulation is ok.. but 

xilinx netlist simulation and target on borad looks like wrong operation...



my condition :
xilinx vertex2 6000
vhdl cpu (so .. mixed language code)
ethamc
synplify
xilinx P&R tools
lxt972 PHY
32MHz system clock
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