Dear All, Currently, I am trying to develop an interface (glue logic) between MAC IP Core and a variable rate data generator (off-chip). My idea is to employ a FIFO between them. Any suggestions and/or source codes (in Verilog) will be strongly appreciated. Regards, Tolga -- To unsubscribe from ethmac mailing list please visit http://www.opencores.org/mailinglists.shtml