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[ethmac] Problems with synthesis of eth_mac

To: ethmac@opencores.org
Subject: [ethmac] Problems with synthesis of eth_mac
From: leorazuk@dcc.ufmg.br
Date: Wed, 9 Jul 2003 22:11:32 -0100
Reply-To: ethmac@opencores.org
Sender: owner-ethmac@opencores.org
Hi everyone,

I am trying to synthetize the eth_mac files using xilinx ISE 4.2i but I am 
having some problems. The following is the message I receive from 
project navigator when trying to do the synthesis:

Writing to hnl 
file 'd:\temp\eth_mac\__express_prj/eth_top/workdirs/WORK/eth_rxaddrc
heck.hnl' 
Warning: The part has fewer I/O ports (166) than that required by the 
design (211)   (FPGA-EXTERNAL-impl-pins-less)
Warning: The port type of port '/eth_top/m_wb_dat_o<31>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<30>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<29>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<28>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<27>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<26>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<25>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<24>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<23>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<22>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<21>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<20>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<19>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<18>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<17>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<16>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<15>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<14>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<13>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<12>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<11>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<10>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<9>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<8>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<7>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<6>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<5>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<4>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<3>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<2>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<1>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
Warning: The port type of port '/eth_top/m_wb_dat_o<0>' is unknown. 
An output pad will be inserted.  (FPGA-pmap-18)
 The output of the cell '/eth_top/miim1/Logic0' is constant. 
 The output of the cell '/eth_top/miim1/Logic1' is constant. 
 The output of the cell '/eth_top/miim1/outctrl/Logic1' is constant. 
 The output of the cell '/eth_top/miim1/outctrl/Logic0' is constant. 
 The output of the cell '/eth_top/miim1/outctrl/cell149' is constant. 
 The output of the cell '/eth_top/miim1/outctrl/cell150' is constant. 
 The output of the cell '/eth_top/miim1/outctrl/cell151' is constant. 
 The output of the cell '/eth_top/miim1/clkgen/Logic1' is constant. 
 The output of the cell '/eth_top/miim1/clkgen/Logic0' is constant. 
 The output of the cell '/eth_top/miim1/clkgen/cell1' is constant. 
 The output of the cell '/eth_top/miim1/clkgen/cell4' is constant. 
 The output of the cell '/eth_top/miim1/clkgen/cell5' is constant. 
 The output of the cell '/eth_top/miim1/cell46' is constant. 
 The output of the cell '/eth_top/Logic1' is constant. 
 The output of the cell '/eth_top/maccontrol1/Logic1' is constant. 
 The output of the cell '/eth_top/maccontrol1/transmitcontrol1/Logic0' is 
constant. 
 The output of the cell '/eth_top/maccontrol1/transmitcontrol1/cell1' is 
constant. 
 The output of the cell '/eth_top/maccontrol1/transmitcontrol1/Logic1' is 
constant. 
 The output of the cell '/eth_top/maccontrol1/transmitcontrol1/cell4' is 
constant. 
 The output of the cell '/eth_top/maccontrol1/receivecontrol1/Logic0' is 
constant. 
 The output of the cell '/eth_top/maccontrol1/receivecontrol1/Logic1' is 
constant. 
 The output of the cell '/eth_top/maccontrol1/receivecontrol1/cell15' is 
constant. 
 The output of the cell '/eth_top/maccontrol1/receivecontrol1/cell18' is 
constant. 
 The output of the cell '/eth_top/maccontrol1/receivecontrol1/cell28' is 
constant. 
 The output of the cell '/eth_top/maccontrol1/receivecontrol1/cell31' is 
constant. 
 The output of the cell '/eth_top/txethmac1/Logic1' is constant. 
 The output of the cell '/eth_top/txethmac1/Logic0' is constant. 
 The output of the cell '/eth_top/txethmac1/cell2' is constant. 
 The output of the cell '/eth_top/txethmac1/txstatem1/cell9' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txstatem1/Logic1' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txstatem1/cell20' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txstatem1/cell22' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txcounters1/Logic1' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txcounters1/Logic0' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txcounters1/cell7' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txcounters1/cell8' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txcounters1/cell9' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txcounters1/cell10' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txcounters1/cell11' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txcounters1/cell19' is 
constant. 
 The output of the cell '/eth_top/txethmac1/random1/Logic0' is 
constant. 
 The output of the cell '/eth_top/txethmac1/random1/Logic1' is 
constant. 
 The output of the cell '/eth_top/txethmac1/random1/cell12' is 
constant. 
 The output of the cell '/eth_top/txethmac1/random1/cell13' is 
constant. 
 The output of the cell '/eth_top/txethmac1/random1/cell14' is 
constant. 
 The output of the cell '/eth_top/txethmac1/random1/cell15' is 
constant. 
 The output of the cell '/eth_top/txethmac1/random1/cell16' is 
constant. 
 The output of the cell '/eth_top/txethmac1/random1/cell17' is 
constant. 
 The output of the cell '/eth_top/txethmac1/random1/cell18' is 
constant. 
 The output of the cell '/eth_top/txethmac1/random1/cell19' is 
constant. 
 The output of the cell '/eth_top/txethmac1/random1/cell20' is 
constant. 
 The output of the cell '/eth_top/txethmac1/txcrc/Logic1' is constant. 
 The output of the cell '/eth_top/wishbone/Logic0' is constant. 
 The output of the cell '/eth_top/wishbone/cell3' is constant. 
 The output of the cell '/eth_top/wishbone/cell7' is constant. 
 The output of the cell '/eth_top/wishbone/cell17' is constant. 
 The output of the cell '/eth_top/wishbone/cell18' is constant. 
 The output of the cell '/eth_top/wishbone/cell19' is constant. 
 The output of the cell '/eth_top/wishbone/cell35' is constant. 
 The output of the cell '/eth_top/wishbone/cell37' is constant. 
 The output of the cell '/eth_top/wishbone/Logic1' is constant. 
 The output of the cell '/eth_top/wishbone/cell56' is constant. 
 The output of the cell '/eth_top/wishbone/cell60' is constant. 
 The output of the cell '/eth_top/wishbone/cell63' is constant. 
 The output of the cell '/eth_top/wishbone/tx_fifo/Logic1' is constant. 
 The output of the cell '/eth_top/wishbone/tx_fifo/Logic0' is constant. 
 The output of the cell '/eth_top/wishbone/tx_fifo/cell4' is constant. 
 The output of the cell '/eth_top/wishbone/tx_fifo/cell8' is constant. 
 The output of the cell '/eth_top/wishbone/tx_fifo/cell9' is constant. 
 The output of the cell '/eth_top/wishbone/cell86' is constant. 
 The output of the cell '/eth_top/wishbone/cell91' is constant. 
 The output of the cell '/eth_top/wishbone/cell102' is constant. 
 The output of the cell '/eth_top/wishbone/rx_fifo/Logic1' is constant. 
 The output of the cell '/eth_top/wishbone/rx_fifo/Logic0' is constant. 
 The output of the cell '/eth_top/wishbone/rx_fifo/cell4' is constant. 
 The output of the cell '/eth_top/wishbone/rx_fifo/cell8' is constant. 
 The output of the cell '/eth_top/wishbone/rx_fifo/cell9' is constant. 
 The output of the cell '/eth_top/wishbone/cell145' is constant. 
 The output of the cell '/eth_top/wishbone/cell148' is constant. 
 The output of the cell '/eth_top/wishbone/cell149' is constant. 
 The output of the cell '/eth_top/wishbone/cell150' is constant. 
 The output of the cell '/eth_top/wishbone/cell157' is constant. 
 The output of the cell '/eth_top/wishbone/cell158' is constant. 
 The output of the cell '/eth_top/wishbone/cell164' is constant. 
 The output of the cell '/eth_top/wishbone/cell179' is constant. 
 The output of the cell '/eth_top/wishbone/cell253' is constant. 
 The output of the cell '/eth_top/wishbone/cell463' is constant. 
 The output of the cell '/eth_top/macstatus1/Logic0' is constant. 
 The output of the cell '/eth_top/macstatus1/Logic1' is constant. 
 The output of the cell '/eth_top/macstatus1/cell6' is constant. 
 The output of the cell '/eth_top/macstatus1/cell10' is constant. 
 The output of the cell '/eth_top/macstatus1/cell11' is constant. 
 The output of the cell '/eth_top/ethreg1/Logic0' is constant. 
 The output of the cell '/eth_top/ethreg1/cell2' is constant. 
 The output of the cell '/eth_top/ethreg1/Logic1' is constant. 
 The output of the cell '/eth_top/ethreg1/cell52' is constant. 
 The output of the cell '/eth_top/ethreg1/cell53' is constant. 
 The output of the cell '/eth_top/rxethmac1/Logic1' is constant. 
 The output of the cell '/eth_top/rxethmac1/Logic0' is constant. 
 The output of the cell '/eth_top/rxethmac1/rxcounters1/Logic0' is 
constant. 
 The output of the cell '/eth_top/rxethmac1/rxcounters1/cell0' is 
constant. 
 The output of the cell '/eth_top/rxethmac1/rxcounters1/Logic1' is 
constant. 
 The output of the cell '/eth_top/rxethmac1/rxcounters1/cell2' is 
constant. 
 The output of the cell '/eth_top/rxethmac1/rxcounters1/cell3' is 
constant. 
 The output of the cell '/eth_top/rxethmac1/rxcounters1/cell4' is 
constant. 
 The output of the cell '/eth_top/rxethmac1/rxcounters1/cell7' is 
constant. 
 The output of the cell '/eth_top/rxethmac1/crcrx/Logic1' is constant. 
 The output of the cell '/eth_top/rxethmac1/cell3' is constant. 
 The output of the cell '/eth_top/rxethmac1/cell6' is constant. 
 The output of the cell '/eth_top/rxethmac1/rxaddrcheck1/Logic1' is 
constant. 
 The output of the cell '/eth_top/rxethmac1/rxaddrcheck1/Logic0' is 
constant. 
 The output of the cell '/eth_top/rxethmac1/rxaddrcheck1/cell2' is 
constant. 
 The output of the cell '/eth_top/rxethmac1/rxaddrcheck1/cell3' is 
constant. 
 The output of the cell '/eth_top/rxethmac1/rxaddrcheck1/cell6' is 
constant. 
Warning: The cell '/eth_top/wishbone/tx_fifo/fifo' is not linked to any 
design.  (FPGA-CHECK-4)
Warning: The cell '/eth_top/wishbone/rx_fifo/fifo' is not linked to any 
design.  (FPGA-CHECK-4)
Warning: The net '/eth_top/m_wb_dat_i<1>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<21>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<7>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<18>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<11>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<25>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<22>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<28>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<31>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<6>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<9>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<23>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<30>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<13>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<16>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<19>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<4>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<26>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<12>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<15>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<27>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/wb_clk_i' may have more than one driver.  
(FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<5>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<2>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<17>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<14>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<10>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<8>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<20>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<0>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<3>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<29>' may have more than one 
driver.  (FPGA-CHECK-10)
Warning: The net '/eth_top/m_wb_dat_i<24>' may have more than one 
driver.  (FPGA-CHECK-10)
Error: The net '/eth_top/wb_clk_i' has more than one driver.  (FPGA-
CHECK-5)
Warning: The net '/eth_top/wishbone/tx_fifo/N507' has no driver. This 
may cause place-and-route  tools to fail.  (FPGA-CHECK-6)
Warning: The net '/eth_top/wishbone/rx_fifo/N507' has no driver. This 
may cause place-and-route  tools to fail.  (FPGA-CHECK-6)
Implementation Errors
Done: failed with exit code: 0001.

At the meantime, where should the eth_cop.v appear at the hierarchy?

Can anyone help me?

Leo.

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