Re: [ethmac] MII Management (MDIO, MDC)

[Maik Boden <maik.boden@gmx.net>]

Novan Hartadi wrote:
> 1. I have a problem to define clock frequency of MDC (interface
>    between PHY and MIIM). I'm not sure what frequency we'll use.
>    If we derive this clock from host, so we must know it.

# MDIO timing relationship to MDC

 - MDIO sourced by STA:  setup time >= 10 ns
                         hold time  >= 10 ns

 - MDIO sourced by PHY:  0 ns <= output delay < 300 ns

The maximum MDC frequency should be 3.33 MHz, right? I think an 3-bit-counter (8
states) driven by TxClk (25 MHz) would provide a MDC frequency of 3.125 MHz. If
you latch incomming data on MDIO at falling edge of TxClk during last state of
counter cycle you might get a delay of 300 ns after rising edge of MDC before
saving the PHY's answer. I'm not sure but it sounds well, or not???


Regards
Maik Boden