[openrisc] OpenRISC vs Altera NIOS

[Steven Grunza <steven_grunza@ieee.org>]

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We are currently evaluating the NIOS processor from Altera and are
looking at the OpenCORE OCR1001 to see if it is comparable for our
intended use.  

The NIOS is ready-to-synthesize and has a C compiler, assembler, and
linker; however, it is only available from Altera and is license
limitted to run only on Altera silicon.  If we can't get the Altera
parts for some reason, even though we have VHDL code for the
processor and all the peripherals, we can't use another
manufacturer's silicon.  For this reason we are checking into the
OpenRISC and LEON processors.

After searching the www.opencores.org site for about a day, I have
not been able to find ready-to-synthesize VHDL for the OCR1001 or any
other OpenRISC core.  The or1k files I have pulled down have various
problems unrelated to the use of the Xylinx RAM lpm's.  If the
OpenRISC cores aren't ready to be used, that's fine.  I just don't
want to report to my manager that they aren't ready if they actually
are ready for use and it's just my inability to find the right code
that is causing the problems.

If anyone has information on how I can get synthesisable VHDL (all
our tools are AHDL or VHDL) for one of the OpenRISC 1000 series
cores, please reply to me at steven_grunza@ieee.org

I have subscribed to the openrisc mailing list but other than the
welcome from majordomo, I haven't seen any traffic on the list (it is
mentioned as being a high traffic list).

Thanks for any help anyone can provide.

Steven Grunza, Hardware Design Engineer

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"Luke, you're going to find that many | Steven Grunza
of the truths we cling to depend      | voice:  (856) 787 - 2759 
greatly on our own point of view."    | fax:    (856) 866 - 2033
 - Obi Wan Kenobi, Return of the Jedi | e-mail: steven_grunza@ieee.org
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