[openrisc] Re: A few quick questions...

[Marko Mlinar <markom@opencores.org>]

Chris Ziomkowski wrote:
> 
> > AE bit in DRR is set, if we have enabled this exception in DSR.
> 
> So what you are saying then, is that we are continuously reading
> the DSR and DRR register waiting for one of them to become
> nonzero? When either one of these conditions is true, then we
> can assume that the processor is halted. Correct?
Actually you have to read only DRR. DSR is for setting which exceptions
stops the processor.
 
> I am still confused however...is this register being set by
> software or by the debug unit? The documentation says it may
> be set by resident debug software or "development interface"
> however it never defines the term "development interface." Is
> this the debug unit or gdb?
By the debug unit - asynchroneously.
Development interface is defined further, I think in or1200 doc.
It is HW and part of RISC (I thought that is obvious since you
are programming its registers). It is connected to TAP (Test
access port), which has also some tracing capabilities. TAP is
connected to JTAG. JTAG is connected to parallel port and then
it or "virtual JTAG" is connected to gdb or1k gdb backend. We've
discussed gdb structure before.
Memory accesses are more complicated: they are routed via TAP and
through wishbone, not through risc. Address space is divided,
so we can access both SPRs and memory through TAP.

> Are you thinking we write monitor software to assist with
> debugging on the CPU, or is this entirely a hardware solution?
> It isn't at all clear how this is designed to be used.
Well this is implementation specific - you should be reading
implementation specs for that. But we will be accessing these
register using TAP. Otherwise you could have remote stub
or something...
BTW: much can also be found in Igor's TAP document.

> What causes the CPU to run after it has been halted? What
> happens at power on or reset? What do I write from the JTAG
> interface to halt the CPU if it is locked in an infinite
> loop? I have read the relevant sections of the manual, but it
> is unclear how this works.

When you set DRR do zero, risc continues.

If you have infinite loop the best is to set ST bit in DMR1.
It is up to us to decide what we will use for debugging,
but you will have to use same procedure as I have for gdb.
Anyway this points are not relevant for you at all.
All you have to do is to implement functionality as explained
in or1k arch and or1200 spec. I will do the debugging part.
You will recieve from me just SPR register and memory reads/writes.

> I think it would help if you could walk me through a typical
> debugging sequence from power up, including downloading of
> code and any interaction with gdb. I can't write a simulator
> until I understand how to simulate it.
As I said, you don't need all that. But anyway:
we expect that board is powered up when we set target.
RISC will do whatever it will do. We will stop it and load
a program in. We also load ourselves sym table.
Then normal gdb session starts (breakpoints, ...).
I explained or1k run/stop above.

> As always, any help you can give me is appreciated.
No problem, but you should read spec as much as you can,
since I don't have enough time walk you through.

Marko