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• R: [openrisc] RTEMS or1k port
  • From: "giuseppe de marco" <gdemarco@unisa.it>
• [openrisc] RTEMS or1k port
  • From: Ivan Guzvinec <ivang@opencores.org>
• Re: [openrisc] Microprocessor or Microcontroller
  • From: "Jim Dempsey" <dempsey@northnet.net>
• R: [openrisc] Microprocessor or Microcontroller
  • From: "giuseppe de marco" <gdemarco@unisa.it>
• Re: [openrisc] Microprocessor or Microcontroller
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] Microprocessor or Microcontroller
  • From: "Sam Gladstone" <samg@t-and-t.com>
• [openrisc] Common memory models integrated into SXP processor
  • From: "Sam Gladstone" <samg@t-and-t.com>
• [openrisc] openrisc automated testing system
  • From: "Damjan Lampret" <lampret@opencores.org>