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[openrisc] Re: Multi layer CPU.

To: openrisc@opencores.org
Subject: [openrisc] Re: Multi layer CPU.
From: test1@yahoo.com
Date: Sat, 8 Dec 2001 14:12:49 +0100
Reply-To: openrisc@opencores.org
Sender: owner-openrisc@opencores.org

Hi
There is a company called "Matrix" that had developed multi layer IC technology that enable "3D-Stacked" circuit layers inside a single chip. The present technology is used for RAM chip, however in the future it is possible to build stacked chips with one layer for CPU circuit, other layers for secondary CPU (SMP), northbridge, southbridge, cache etc. Is it possible to use this technology with OpenRISC CPU?
Regards

http://www.matrixsemi.com/3dtech.shtml?26

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