[openrisc] Re: OR1000 16 bit instruction set

[Andreas Bombe <bombe@informatik.tu-muenchen.de>]

List ate my email - this is a resend.

On Thu, Feb 14, 2002 at 08:43:44PM +0100, Damjan Lampret wrote:
> Hi Jeff,
> 
> it is all about demand. Right now it looks like 32-bit insn length is most
> wanted, especially because of the coming 64-bit superscalar version of the
> OR1K. It is also true that prices of Flash and RAM are droping some 30% or
> more each year. But if there will be enough interest for 16-bit insn length,
> it could become a priority.

"Whatever, RAM is cheap these days" is the usual answer, but usually
cost per MB is not the issue.  It is the wrong answer on desktop systems
(because RAM is slow) and usually wrong in low cost embedded systems.

Think low cost => small pin count package => max. 16 bit data path to
RAM => two fetches per insn.  Also little space => max. CPU + one SDRAM
+ one flash => 16 bit data bus.  16 bit is the maximum you can actually
get for a single SDRAM it seems, and even then 8 and less bits SDRAMs
may be more common (and cheaper).

I saw a statistic for ARM somewhere, Thumb was about comparable in speed
(or slightly slower, not sure) to ARM on a full 32 bit architecture but
significantly faster on 16 bit ROM/RAM.


Heh, I don't want to tell you what to do, I guess I just feel offended
by the "RAM is cheap" mindset ;-)

-- 
Andreas Bombe <bombe@informatik.tu-muenchen.de>    DSA key 0x04880A44
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