Re: [openrisc] Re: PC as GPR?

["Jim Dempsey" <tapedisk@ameritech.net>]

----- Original Message ----- 
From: "Marko Mlinar" <markom@opencores.org>
To: <openrisc@opencores.org>
Sent: Tuesday, February 26, 2002 1:55 AM
Subject: Re: [openrisc] Re: PC as GPR?

> > It also makes moving memory operations a pain - strcmp, memset, ...
> Yes, post increment would be very useful here.
> Maybe block transfer instruction would be useful; e.g.:
> l.sw (r1),r9,r10,r12,r14
> But it would really be nice if it could be cache line aligned.
> 

You are using a PLD here, aren't you? Part of this discussion also
touched on adding floating point and other instructions. I would
think that a generic instruction extension capability would be in
order. Something like that in the NIOS processor. Or if that
doesn't fit in with the design then consider the Escape sequence
used on the 8086 and like processors. For the string instructions
and block operations you would incorporate the instructions in
logic using possibly a DMA core in conjunction with a limited
FIFO (to byte align the operations). QED

Jim


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