Re: [openrisc] Breakpoints + Development interface

[Marko Mlinar <markom@opencores.org>]

> 1- Does the actual OR1200 implementation has any programmable way (named
> breakpoint or not) to freeze the processor at any time and/or on any
> instruction? I'm not interested on approaches that halt the processor using
> a special instruction. I really need to stop it during the normal flow,
> without previously inserting special instructions in the middle.
Although or1200 does not have full debugging support as specified in 
architecture, it has l.trap instruction, program loading, SoC bus access, 
stalling capabitilites, etc. which offer full debugging capabilities.
There is also gdb support for it.

> 2- Does the solution to 1) allows us to get the processor control through
> its development interface? How the outside world is notified about such
> event?
yes.

> 3- Does the current OR1200 implementation follows the recent "SoC/OpenRISC
> Development Interface" from Igor?
yes.

> 4- Does anyone can point me a processor/ASIC (open source or not) that has
> breakpoint support and a development interface (On Chip Debugging) based on
> IEEE 1149.1 JTAG similar to the one Igor specifies, with rich internal
> scan-chains? (I know that Atmel has an ERC32 variant named TSC695E but ...
> it is very expensive and the core isn't open sourced. Motorola also use the
> same OCD method on the PowerPC. Unfortunately, in this case the internal
> scan chain information is only provided to Emulator vendors under a NDA.)
The nice benefit of our solution, is by my opinion price. Commercial 
developement systems costs several $10000, while our is free and it has all 
you need. And if you need more or any proprietary functions, you are not 
limited, since you have the source code.

Marko

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