[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [openrisc] OR1200 implementation of l.sb and l.sh
On Thursday 23 January 2003 12:30, Marko Mlinar wrote:
> On Thursday 23 January 2003 11:50, Marķa Bolado wrote:
> > Hi!
> >
> > I've been looking at the OR1200 rtl, and I've seen that when a l.sb insn,
> > i.e,
> >
> > l.sb 0(r4), r5 // EA <- 0 + r4
> > // (EA) <- r5[7:0]
> >
> > or1200 writes a whole (re-ordinated) 32-bit word in cache. Thus, when you
> > only want to write the byte 3 of a particular word, you are also writing
> > bytes 0, 1 and 2, so the rest of the bytes of the word are modified in
> > cache, though they mustn't.
> >
> > Could you please clear up this point?
>
> What you stated is correct, except proper select bits are set on Wishbone
> bus,
Yes, I agree, but that bits are used by main memory, and I am talking about
cache memory.
> so when writing one byte, you just write one byte, although you put
> whole word on wishbone data bus.
In or1200 data cache doesn't use that selection bits, so I wonder how it can
know if it has to write a byte, a half word or a whole word.
Best wishes,
Marķa Bolado
--
To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml